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authorPatrick Rudolph <patrick.rudolph@9elements.com>2019-07-11 16:21:15 +0200
committerPatrick Rudolph <siro@das-labor.org>2019-07-15 07:14:57 +0000
commit96d8e4317835ed490a3999f173c50a2c0a36314a (patch)
tree0382addc1c7f5f629b1d270c162276d39e60983a /Documentation/soc
parent6eccc99b9c652f3221dd1aee875728b2307979aa (diff)
downloadcoreboot-96d8e4317835ed490a3999f173c50a2c0a36314a.tar.xz
Documentation: Add FSP bugs
As Intel doesn't even document known bugs add a list of FSP bugs here. Change-Id: I07819b83fb0c9437fc237472dfe943f78738347a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34239 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/soc')
-rw-r--r--Documentation/soc/intel/fsp/index.md43
1 files changed, 43 insertions, 0 deletions
diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md
index d7f44c6dee..6269445ff3 100644
--- a/Documentation/soc/intel/fsp/index.md
+++ b/Documentation/soc/intel/fsp/index.md
@@ -2,6 +2,39 @@
This section contains documentation about Intel-FSP in public domain.
+## Bugs
+As Intel doesn't even list known bugs, they are collected here until
+those are fixed. If possible a workaround is described here as well.
+
+### BroadwellDEFsp
+
+* IA32_FEATURE_CONTROL MSR is locked in FSP-M
+ * Release MR2
+ * Writing the MSR is required in ramstage for Intel TXT
+ * Workaround: none
+ * Issue on public tracker: [Issue 10]
+
+* FSP-S asserts if the thermal PCI device 00:1f.6 is disabled
+ * Release MR2
+ * FSP expects the PCI device to be enabled
+ * FSP expects BARs to be properly assigned
+ * Workaround: Don't disable this PCI device
+ * Issue on public tracker: [Issue 13]
+
+### KabylakeFsp
+* MfgId and ModulePartNum in the DIMM_INFO struct are empty
+ * Release 3.7.1
+ * Those values are typically consumed by SMBIOS type 17
+ * Workaround: none
+ * Issue on public tracker: [Issue 22]
+
+### BraswellFsp
+* Internal UART can't be disabled using PcdEnableHsuart*
+ * Release MR2
+ * Workaround: Disable internal UART manually after calling FSP
+ * Issue on public tracker: [Issue 10]
+
+
## Open Source Intel FSP specification
* [About Intel FSP](https://firmware.intel.com/learn/fsp/about-intel-fsp)
@@ -15,3 +48,13 @@ This section contains documentation about Intel-FSP in public domain.
## Additional Features in FSP 2.1 specification
- [PPI](ppi/ppi.md)
+
+## Official bugtracker
+
+- [IntelFSP/FSP](https://github.com/IntelFsp/FSP/issues)
+
+[Issue 10]: https://github.com/IntelFsp/FSP/issues/10
+[Issue 13]: https://github.com/IntelFsp/FSP/issues/13
+[Issue 15]: https://github.com/IntelFsp/FSP/issues/15
+[Issue 22]: https://github.com/IntelFsp/FSP/issues/22
+