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authorPatrick Rudolph <patrick.rudolph@9elements.com>2020-04-15 11:19:31 +0200
committerPatrick Rudolph <siro@das-labor.org>2020-08-18 05:53:43 +0000
commit49ae596a5907bd545e344d540004d05a7ff000e0 (patch)
tree8096d6acf6eef86e2cd942604f2296908c930c45 /Documentation/soc
parent6dbec2d81b2d6fcfacfb94ca7e2c319366597a5c (diff)
downloadcoreboot-49ae596a5907bd545e344d540004d05a7ff000e0.tar.xz
soc/intel/common: Add support for LPSS UART in ACPI mode
Emit ACPI code for LPSS UARTs operating in ACPI mode. In this mode the device vendor ID reads as 0xffff, the PCI devices is still operate. Add ACPI device IDs for APL, GLK, SPT, SPT_H and CNP_H. The mainboard's devicetree needs to be adapted to include the chip driver and the PCI ID when it wouldn't have been hidden. Example: chip soc/intel/common/block/uart device pci 19.2 hidden register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2" end # UART #2 end Tested on Linux 5.6 with Sunrise Point ACPI ID for UART2. Tested on Windows for all other UARTs. Change-Id: I838d16322be38f5421c1f63b457a0af552e0ed96 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40405 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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