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| author | Philip Chen <philipchen@google.com> | 2019-04-29 10:18:24 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-15 17:47:13 +0000 |
| commit | 0d4200fef396fb0d1fbf28b4ced475fbf59b5b85 (patch) | |
| tree | 4cfd6a29afa5062c4bb125320657e7b54f6f002c /Documentation | |
| parent | 72f6fbb1bc64a68dab121231b186c803e9836ad7 (diff) | |
| download | coreboot-0d4200fef396fb0d1fbf28b4ced475fbf59b5b85.tar.xz | |
soc/intel/cannonlake: Support different SPD read type for each slot
Also clean up cannonlake_memcfg_init.
The major changes include:
(1) Add enum 'mem_info_read_type' to spd_info.
(2) Add per-dimm-slot spd_info to cnl_mb_cfg.
(3) Setup memory config for each slot independently.
(4) Squash meminit_memcfg_spd().
BUG=chromium:960581, b:124990009
BRANCH=none
TEST=boot hatch, hatch_whl, and kohaku
Change-Id: I686a85996858204c20fd05ef24787a0487817c34
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32513
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions