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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-06-08 07:11:48 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-06-09 17:42:12 +0200 |
| commit | 3892597349cdbdf5378718ceb03dbbc53f5d543a (patch) | |
| tree | 400d75aeff7e5c560b591be27624c2c0f8fef1eb /Documentation | |
| parent | 538b324c5f6e890b435dd88f4674cdd09fb56ed9 (diff) | |
| download | coreboot-3892597349cdbdf5378718ceb03dbbc53f5d543a.tar.xz | |
arch/x86: Enable SSE in bootblock_crt0.S
Don't write reserved bits in the Quark platform. Follow the previous
boot behavior and just enable SSE.
TEST=Build and run on Galileo Gen2
Change-Id: Ib3143eff02b2610b595bd666c10d70e43103ccda
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15128
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions