diff options
| author | Nico Huber <nico.h@gmx.de> | 2018-11-13 19:28:07 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-23 08:34:16 +0000 |
| commit | d67edcae6e9d438f2e60f6b67d97a7d3f09cb18b (patch) | |
| tree | 38d7fe7b769f4193ea3b4494dc7944b9718c678c /Documentation | |
| parent | 3032d7677883eb726d14fcd85efae7a7c068259a (diff) | |
| download | coreboot-d67edcae6e9d438f2e60f6b67d97a7d3f09cb18b.tar.xz | |
soc/intel/common: Bring DISPLAY_MTRRS into the light
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the
"Debug" menu. It turned out, though, that the code looks rather generic.
No need to hide it in soc/intel/.
To not bloat src/Kconfig up any further, start a new `Kconfig.debug`
hierarchy just for debug options.
If somebody wants to review the code if it's 100% generic, we could
even get rid of HAVE_DISPLAY_MTRRS.
Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29684
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/Intel/Board/Galileo_checklist.html | 2 | ||||
| -rw-r--r-- | Documentation/Intel/SoC/soc.html | 2 |
2 files changed, 0 insertions, 4 deletions
diff --git a/Documentation/Intel/Board/Galileo_checklist.html b/Documentation/Intel/Board/Galileo_checklist.html index 3fc04b18ce..397f570b0e 100644 --- a/Documentation/Intel/Board/Galileo_checklist.html +++ b/Documentation/Intel/Board/Galileo_checklist.html @@ -79,8 +79,6 @@ <tr bgcolor=#ffc0c0><td>Required</td><td>smm_region_size</td></tr> <tr bgcolor=#c0ffc0><td>Required</td><td>soc_after_ram_init</td></tr> <tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_memory_init_params</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_mtrrs</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>soc_get_variable_mtrr_count</td></tr> <tr bgcolor=#c0ffc0><td>Required</td><td>soc_memory_init_params</td></tr> <tr bgcolor=#ffffc0><td>Optional</td><td>soc_pre_ram_init</td></tr> <tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr> diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 29b819ec82..fff536b9b1 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -234,8 +234,6 @@ Use the following steps to locate the FSP binary: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc">src/drivers/intel/fsp1_1/cache_as_ram.inc</a> </li> <li>Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common - specifically building - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/common/util.c">util.c</a> </li> </ol> </li> |