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| author | Dmitry Torokhov <dtor@chromium.org> | 2021-03-10 11:16:27 -0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-03-11 22:38:52 +0000 |
| commit | 39c1b4f951f77649ef86ffece8f9bd2f963c8484 (patch) | |
| tree | a20c73985041f08cdca82244f5f86e86e18a2ecc /Documentation | |
| parent | a70d17dba242d498cc2bb5b63881911c6e9bd113 (diff) | |
| download | coreboot-39c1b4f951f77649ef86ffece8f9bd2f963c8484.tar.xz | |
Documentation/acpi: switch example from edge to level interrupts
Configuring touch controllers to use edge-triggered interrupts is not
recommended as it is very easy to lose an edge when kernel drivers
disable the interrupt for one reason or another, and recovering from
this condition requires workarounds in the kernel.
Unfortunately the example setting up a touchpad used edge-triggered
interrupts, and this set up has been propagating through the boards.
Let's switch the example to use level interrupts instead.
Change-Id: I4dc8b91ed070ce117553b00a087ad709aeaf16af
Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/acpi/devicetree.md | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/Documentation/acpi/devicetree.md b/Documentation/acpi/devicetree.md index e8680e359f..f121698ed5 100644 --- a/Documentation/acpi/devicetree.md +++ b/Documentation/acpi/devicetree.md @@ -30,7 +30,7 @@ device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" device i2c 15 on end end @@ -60,7 +60,7 @@ Scope (\_SB.PCI0.I2C0) I2cSerialBusV2 (0x0015, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.I2C0", 0x00, ResourceConsumer, , Exclusive, ) - Interrupt (ResourceConsumer, Edge, ActiveLow, ExclusiveAndWake, ,, ) + Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, ,, ) { 0x0000002D, } @@ -136,7 +136,7 @@ corresponds to **const char *desc** and in ASL: It also adds the interrupt, ``` - Interrupt (ResourceConsumer, Edge, ActiveLow, ExclusiveAndWake, ,, ) + Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, ,, ) { 0x0000002D, } @@ -145,15 +145,15 @@ It also adds the interrupt, which comes from: ``` - register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" ``` -The GPIO pin IRQ settings control the "Edge", "ActiveLow", and -"ExclusiveAndWake" settings seen above (edge means it is an edge-triggered -interrupt as opposed to level-triggered; active low means the interrupt is -triggered on a falling edge). +The GPIO pin IRQ settings control the "Level", "ActiveLow", and +"ExclusiveAndWake" settings seen above (level means it is a level-triggered +interrupt as opposed to edge-triggered; active low means the interrupt is +triggered when the signal is low). -Note that the ACPI_IRQ_WAKE_EDGE_LOW macro informs the platform that the GPIO +Note that the ACPI_IRQ_WAKE_LEVEL_LOW macro informs the platform that the GPIO will be routed through SCI (ACPI's System Control Interrupt) for use as a wake source. Also note that the IRQ names are SoC-specific, and you will need to find the names in your SoC's header file. The ACPI_* macros are defined in |