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| author | Jeremy Soller <jeremy@system76.com> | 2019-02-20 16:39:55 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-17 08:24:09 +0000 |
| commit | 1af482c9c9679cb7a6b54dfd74c88eb4c9ee8de5 (patch) | |
| tree | 4ebd3ec0afb22366b9523ff65710b0af9e7eb51a /Documentation | |
| parent | b6e2afb1ffe7683118ba879ca19ef6343f641d17 (diff) | |
| download | coreboot-1af482c9c9679cb7a6b54dfd74c88eb4c9ee8de5.tar.xz | |
soc/intel/cannonlake: Set correct serirq mode
Set FSP params PchSirqEnable/PchSirqMode based on board
setting of serirq_mode. Matches implementation on Skylake.
This is a no-change for existing boards since the default
remains SERIRQ_QUIET mode.
Tested on system76 galp3-c, out-of-tree WHL-U board
Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Nathaniel L Desimone <nathaniel.l.desimone@intel.com>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions