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authorPaul Menzel <pmenzel@molgen.mpg.de>2019-09-20 10:09:12 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-11-19 12:57:28 +0000
commit44b54aa947caedef662e5401f006e96f58d1f70d (patch)
tree218ca7f6b9819b3db68a3ec24b4381cf95770044 /Documentation
parent53b549c43d97cebda68902ddcb9737e074a667c9 (diff)
downloadcoreboot-44b54aa947caedef662e5401f006e96f58d1f70d.tar.xz
Documentation: Reword Supermicro X10SLM+-F datasheet references
Change-Id: I24c4254ef65edcddadcf0386e0cbe996a5e99458 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/mainboard/supermicro/x10slm-f.md5
1 files changed, 2 insertions, 3 deletions
diff --git a/Documentation/mainboard/supermicro/x10slm-f.md b/Documentation/mainboard/supermicro/x10slm-f.md
index acb2c84fa2..703608028a 100644
--- a/Documentation/mainboard/supermicro/x10slm-f.md
+++ b/Documentation/mainboard/supermicro/x10slm-f.md
@@ -68,7 +68,7 @@ region is not readable even by the host.
The main firmware flash chip is an SOIC-8 package located near the CMOS
battery and SATA ports. It should come with a sticker attached that
states the firmware revision (e.g. "X10SLH 4.424"). The chip model is
-an N25Q128A, and the datasheet can be found [here][N25Q128A].
+an N25Q128A ([datasheet][N25Q128A]).
As with [internal programming](#internal-programming), [flashrom] works
reliably:
@@ -87,8 +87,7 @@ way without issue.
This board has an ASPEED [AST2400], which has BMC functionality. The
BMC firmware resides in a 32 MiB SOIC-16 chip just above the [AST2400].
-This chip is an MX25L25635F, whose datasheet can be found
-[here][MX25L25635F].
+This chip is an MX25L25635F ([datasheet][MX25L25635F]).
### Removing the BMC functionality