sc7180: Provide initial SoC support

Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

3 files changed, 27 insertions, 0 deletions

diff --git a/Documentation/soc/index.md b/Documentation/soc/index.md
index fccddbd025..1415c721bb 100644
--- a/Documentation/soc/index.md
+++ b/Documentation/soc/index.md
@@ -7,3 +7,4 @@ This section contains documentation about coreboot on specific SOCs.
 - [AMD](amd/index.md)
 - [Cavium](cavium/index.md)
 - [Intel](intel/index.md)
+- [Qualcomm](qualcomm/index.md)
diff --git a/Documentation/soc/qualcomm/index.md b/Documentation/soc/qualcomm/index.md
new file mode 100644
index 0000000000..5cd79819bd
--- /dev/null
+++ b/Documentation/soc/qualcomm/index.md
@@ -0,0 +1,7 @@
+# Qualcomm SOC-specific documentation
+
+This section contains documentation about coreboot on specific Qualcomm SOCs.
+
+## Platforms
+
+- [SC7180 series](sc7180/index.md)
diff --git a/Documentation/soc/qualcomm/sc7180/index.md b/Documentation/soc/qualcomm/sc7180/index.md
new file mode 100644
index 0000000000..8f5d33d8c4
--- /dev/null
+++ b/Documentation/soc/qualcomm/sc7180/index.md
@@ -0,0 +1,19 @@
+# Qualcomm SC7180 documentation
+
+## SOC code
+
+The SOC folder contains functions for:
+* MMU
+* CLOCK
+* GPIO
+* QUPv3 FW (provides a bridge to serial interfaces)
+* UART
+* SPI-NOR
+* AOP FW
+* USB
+
+## Notes about the hardware
+
+The timer is used from the ARMv8 architecture specific code.
+
+