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authorAngel Pons <th3fanbus@gmail.com>2018-08-28 20:37:58 +0200
committerMartin Roth <martinroth@google.com>2018-08-30 14:47:41 +0000
commit8120759d90f7e5164a600f21bdd04b8878ba8259 (patch)
tree1bb6ad18fc2c5fe5d299789b822363e8ad2e54b5 /Documentation
parent0805cbe6ae37e563dadaae2e9c01f4ca383393fb (diff)
downloadcoreboot-8120759d90f7e5164a600f21bdd04b8878ba8259.tar.xz
Documentation/nb/intel/sandybridge/nri_registers.md: Fix mistake
According to a comment on fa1a07b, the 100MHz clock is the Ivy Bridge only clock, not the 133MHz one. Change-Id: I28fed4a9264b96f93b9e88325f547a5db512514c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28377 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/northbridge/intel/sandybridge/nri_registers.md4
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md
index d5857ec615..aa16644b17 100644
--- a/Documentation/northbridge/intel/sandybridge/nri_registers.md
+++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md
@@ -2137,8 +2137,8 @@ Please handle with care !
+===========+==================================================================+
| 0:7| Selected multiplier: 100Mhz [7,12], 133Mhz [3,19] |
+-----------+------------------------------------------------------------------+
-| 8 | - 1: 100Mhz reference clock |
-| | - 0: 133Mhz reference clock (Ivy Bridge only) |
+| 8 | - 1: 100Mhz reference clock (Ivy Bridge only) |
+| | - 0: 133Mhz reference clock |
+-----------+------------------------------------------------------------------+
| 31 | PLL busy |
+-----------+------------------------------------------------------------------+