diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-01-07 11:24:24 -0800 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-02-02 15:54:43 +0100 |
| commit | c1e4f8995362c6eb7d09dfc0618edcc636d30acc (patch) | |
| tree | f5639a152232579412a3a9da0e4cd224f30505e8 /Documentation | |
| parent | 2f91403303a66c5e724761a74863e3452291b154 (diff) | |
| download | coreboot-c1e4f8995362c6eb7d09dfc0618edcc636d30acc.tar.xz | |
Documentation: Add x86 documentation for required files
Document the required files to perform a minimal coreboot/FSP build for
x86.
TEST=None
Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13438
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/Intel/Board/board.html | 83 | ||||
| -rw-r--r-- | Documentation/Intel/Board/galileo.html | 100 | ||||
| -rw-r--r-- | Documentation/Intel/SoC/quark.html | 98 | ||||
| -rw-r--r-- | Documentation/Intel/SoC/soc.html | 105 | ||||
| -rw-r--r-- | Documentation/Intel/development.html | 78 | ||||
| -rw-r--r-- | Documentation/Intel/fsp1_1.html | 50 | ||||
| -rw-r--r-- | Documentation/Intel/index.html | 42 |
7 files changed, 556 insertions, 0 deletions
diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html new file mode 100644 index 0000000000..e43985c62d --- /dev/null +++ b/Documentation/Intel/Board/board.html @@ -0,0 +1,83 @@ +<!DOCTYPE html> +<html> + <head> + <title>Board</title> + </head> + <body> + +<h1>x86 Board Development</h1> +<p> + Board development requires System-on-a-Chip (SoC) support. + The combined steps are listed + <a target="_blank" href="../x86Development.html">here</a>. + The development steps for the board are listed below: +</p> +<ol> + <li><a href="#RequiredFiles">Required Files</a></li> +</ol> + + +<hr> +<h1><a name="RequiredFiles">Required Files</a></h1> +<p> + Create the board directory as src/mainboard/<Vendor>/<Board>. +</p> + +<p> + The following files are required to build a new board: +</p> +<ol> + <li>Kconfig.name - Defines the Kconfig value for the board</li> + <li>Kconfig + <ol type="A"> + <li>Selects the SoC for the board and specifies the SPI flash size + <ol type="I"> + <li>BOARD_ROMSIZE_KB_<Size></li> + <li>SOC_<Vendor>_<Chip Family></li> + </ol> + </li> + <li>Declare the Kconfig values for: + <ol type="I"> + <li>MAINBOARD_DIR</li> + <li>MAINBOARD_PART_NUMBER</li> + <li>MAINBOARD_VENDOR</li> + </ol> + </li> + </ol> + </li> + <li>devicetree.cb - Enable root bridge and serial port + <ol type="A"> + <li>The first line must be "chip soc/Intel/<soc family>"; + this path is used by the generated static.c to include the chip.h + header file + </li> + </ol> + </li> + <li>romstage.c + <ol type="A"> + <li>Add routine mainboard_romstage_entry which calls romstage_common</li> + </ol> + </li> + <li>Configure coreboot build: + <ol type="A"> + <li>Set LOCALVERSION</li> + <li>FLASHMAP_OFFSET = 0x00700000</li> + <li>Select vendor for the board</li> + <li>Select the board</li> + <li>CBFS_SIZE = 0x00100000</li> + <li>Set the CPU_MICROCODE_CBFS_LEN</li> + <li>Set the CPU_MICROCODE_CBFS_LOC</li> + <li>Set the FSP_IMAGE_ID_STRING</li> + <li>Set the FSP_LOC</li> + <li>Disable GOP_SUPPORT</li> + <li>No payload</li> + <li>Choose the default value for all other options</li> + </ol> + </li> +</ol> + + +<hr> +<p>Modified: 31 January 2016</p> + </body> +</html>
\ No newline at end of file diff --git a/Documentation/Intel/Board/galileo.html b/Documentation/Intel/Board/galileo.html new file mode 100644 index 0000000000..210a821b41 --- /dev/null +++ b/Documentation/Intel/Board/galileo.html @@ -0,0 +1,100 @@ +<!DOCTYPE html> +<html> + <head> + <title>Galileo Gen 2</title> + </head> + <body> + +<h1>Intel® Galileo Gen 2 Development Board</h1> +<table> + <tr> + <td><a target="_blank" href="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg"><img alt="Galileo Gen 2" src="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg" width=500></a></td> + <td> +<table> + <tr bgcolor="#ffc0c0"> + <td> +Warning: Use of the Intel® Galileo Gen 2 mainboard code requires modification of the +util/xcompile/xcompile file to change the machine architecture from i686 to i586 because +the Quark™ processor does not support the instructions introduced with the +Pentium™ 6 architecture. +<ol> + <li>Edit the file util/xcompile/xcompile</li> + <li>Search for +<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=util/xcompile/xcompile;hb=HEAD#l185">-march</a></li> + <li>Replace i686 with i586</li> + <li>Save the result</li> +</ol> +Without this change the Quark™ processor will halt when it executes one of the +instructions introduced with the Pentium™ 6 architecture. + </td> + </tr> +</table> +<p> + The Intel® Galileo Gen 2 mainboard code was developed along with the Intel® + <a target="_blank" href="../SoC/quark.html">Quark™</a> SoC: +</p> +<ul> + <li><a target="_blank" href="../x86Development.html">Overall</a> development</li> + <li><a target="_blank" href="../SoC/soc.html">SoC</a> support</li> + <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> + <li><a target="_blank" href="board.html">Board</a> support</li> +</ul> + </td> + </tr> +</table> + + + +<hr> +<h1>Galileo Gen 2 Board Documentation</h1> +<ul> + <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_blockdiagram.jpg">Block Diagram</a></li> + <li><a target="_blank" href="https://software.intel.com/en-us/iot/library/galileo-getting-started">Getting Started</a></li> + <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/galileo/galileo-overview.html">Overview</a></li> + <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_ports.jpg">Port Diagram</a></li> + <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/intelgalileogen2prodbrief_330736_003.pdf">Product Brief</a></li> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-g2-schematic.pdf">Schematic</a></li> + <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/galileo_boarduserguide_330237_001.pdf">User Guide</a></li> + <li>Components + <ul> + <li>A/D: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/adc108s102.pdf">ADC108S102</a></li> + <li>Analog Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/ts5a23159.pdf">TS5A23159</a></li> + <li>Ethernet (10/100 MB/S): Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/dp83848-ep.pdf">DP83848</a></li> + <li>Load Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps22920.pdf">TPS22920x</a></li> + <li>Memory (256 MiB): Micron <a target="_blank" href="https://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/DDR3/1Gb_1_35V_DDR3L.pdf">MT41K128M8</a></li> + <li>SoC: Intel® Quark™ <a target="_blank" href="../SoC/quark.html">X-1000</a></li> + <li>Serial EEPROM (1 KiB): ON Semiconductor® <a target="_blank" href="http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF">CAT24C08</a></li> + <li>SPI Flash (8 MiB): Winbond™ <a target="_blank" href="http://www.winbond-usa.com/resource-files/w25q64fv_revl1_100713.pdf">W25Q64FV</a></li> + <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf">TPS62130</a></li> + <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ug/slvu570/slvu570.pdf">TPS652510</a></li> + <li>Termination Regulator: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps51200.pdf">TPS51200</a></li> + </ul> + </li> +</ul> + + + +<hr> +<h1>Debug Tools</h1> +<ul> + <li>Flash Programmer: + <ul> + <li>Dediprog <a target="_blank" href="http://www.dediprog.com/pd/spi-flash-solution/SF100">SF100</a> ISP IC Programmer</li> + </ul> + </li> + <li>JTAG Connector: <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=Olimex+ARM-JTAG-20-10">Olimex ARM-JTAG-20-10</a></li> + <li>JTAG Debugger: + <ul> + <li>Olimex LTD <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=Olimex+ARM-USB-OCD-H">ARM-USB-OCD-H</a></li> + <li>Tincan Tools <a target="_blank" href="https://www.tincantools.com/wiki/Flyswatter2">Flyswatter2</a></li> + </ul> + </li> + <li><a target="_blank" href="http://download.intel.com/support/processors/quark/sb/sourcedebugusingopenocd_quark_appnote_330015_003.pdf">Hardware Setup and Software Installation</a></li> + <li>USB Serial cable: FTDI <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=FTDI+TTL-232R-3V3">TTL-232R-3V3</a></li> +</ul> + + +<hr> +<p>Modified: 30 January 2016</p> + </body> +</html> diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html new file mode 100644 index 0000000000..14dd5076b3 --- /dev/null +++ b/Documentation/Intel/SoC/quark.html @@ -0,0 +1,98 @@ +<!DOCTYPE html> +<html> + <head> + <title>Quark™ SoC</title> + </head> + <body> + +<h1>Intel® Quark™ SoC</h1> +<table> + <tr> + <td><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png"><img alt="Quark Block Diagram" src="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png" width=500></a></td> + <td> +<table> + <tr bgcolor="#ffc0c0"> + <td> +Warning: Use of the Intel® Quark™ SoC code requires modification of the util/xcompile/xcompile file to change the machine +architecture from i686 to i586 because the Quark™ processor does not support the instructions +introduced with the Pentium™ 6 architecture. +<ol> + <li>Edit the file util/xcompile/xcompile</li> + <li>Search for +<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=util/xcompile/xcompile;hb=HEAD#l185">-march</a></li> + <li>Replace i686 with i586</li> + <li>Save the result</li> +</ol> +Without this change the Quark™ processor will halt when it executes one of the +instructions introduced with the Pentium™ 6 architecture. + </td> + </tr> +</table> +<p> + The Quark™ SoC code was developed using the + <a target="_blank" href="../Board/galileo.html">Galileo Gen 2</a> + board: +</p> +<ul> + <li><a target="_blank" href="../x86Development.html">Overall</a> development</li> + <li><a target="_blank" href="soc.html">SoC</a> support</li> + <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> + <li><a target="_blank" href="../Board/board.html">Board</a> support</li> +</ul> + </td> + </tr> +</table> + + + +<hr> +<h1>Quark™ Documentation</h1> +<ul> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png">Block Diagram</a></li> + <li>Intel® 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf">Software Developer Manual</a></li> + <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/quark/specifications.html">Specifications</a>: + <ul> + <li><a target="_blank" href="http://ark.intel.com/products/79084/Intel-Quark-SoC-X1000-16K-Cache-400-MHz">X1000</a> + - <a target="_blank" href="http://www.intel.com/content/www/us/en/search.html?keyword=X1000">Documentation</a>: + <ul> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/quark-x1000-datasheet.pdf">Datasheet</a></li> + <li><a target="_blank" href="http://www.intel.com/content/dam/support/us/en/documents/processors/quark/sb/intelquarkcore_devman_001.pdf">Developer's Manual</a></li> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/intel-quark-product-brief-v3.pdf">Product Brief</a></li> + </ul> + </li> + </ul> + </li> +</ul> + + + +<hr> +<h1>Quark™ FSP</h1> +<ul> + <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li> + <li>Intel® Quark™ SoC X1000 <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/quark-x1000-uefi-firmware-writers-guide.pdf">UEFI Firmware Writer's Guide</a></li> + <li>EDK2 Sources: + <ul> + <li>EDK2: git clone <a target="_blank" href="https://github.com/tianocore/edk2.git">https://github.com/tianocore/edk2.git</a></li> + <li>EDK2-FatPkg: git clone <a target="_blank" href="https://github.com/tianocore/edk2-FatPkg.git">https://github.com/tianocore/edk2-FatPkg.git</a> FatPkg</li> + <li>EDK2-non-osi: git clone <a target="_blank" href="https://github.com/tianocore/edk2-non-osi.git">https://github.com/tianocore/edk2-non-osi.git</a></li> + <li>Win32 BaseTools: git clone <a target="_blank" href="https://github.com/tianocore/edk2-BaseTools-win32.git">https://github.com/tianocore/edk2-BaseTools-win32.git</a></li> + </ul> + </li> + <li>Win32 Build Instructions: +<pre><code>set WORKSPACE=%CD% +set PACKAGES_PATH=%WORKSPACE%\edk2;%WORKSPACE%\FatPkg;%WORKSPACE%\edk2-non-osi +set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32 +cd edk2 +edksetup.bat +build -p QuarkPlatformPkg/Quark.dsc -a IA32 -t VS2012x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 +</code></pre> + </li> +</ul> + + + +<hr> +<p>Modified: 30 January 2016</p> + </body> +</html>
\ No newline at end of file diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html new file mode 100644 index 0000000000..30821dcd9c --- /dev/null +++ b/Documentation/Intel/SoC/soc.html @@ -0,0 +1,105 @@ +<!DOCTYPE html> +<html> + <head> + <title>SoC</title> + </head> + <body> + +<h1>x86 System on a Chip (SoC) Development</h1> +<p> + SoC development is best done in parallel with development for a specific + board. The combined steps are listed + <a target="_blank" href="../x86Development.html">here</a>. + The development steps for the SoC are listed below: +</p> +<ol> + <li><a target="_blank" href="../fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li> + <li>SoC <a href="#RequiredFiles">Required Files</a></li> + <li><a href="#Descriptor">Start Booting</a></li> + <li><a href="#EarlyDebug">Early Debug</a></li> +</ol> + + +<hr> +<h1><a name="RequiredFiles">Required Files</a></h1> +<p> + Create the directory as src/soc/<Vendor>/<Chip Family>. +</p> + +<p> + The following files are required to build a new SoC: +</p> +<ul> + <li>Include files + <ul> + <li>include/soc/pei_data.h</li> + <li>include/soc/pm.h</li> + </ul> + </li> + <li>Kconfig - Defines the Kconfig value for the SoC and selects the tool + chains for the various stages: + <ul> + <li>select ARCH_BOOTBLOCK_<Tool Chain></li> + <li>select ARCH_RAMSTAGE_<Tool Chain></li> + <li>select ARCH_ROMSTAGE_<Tool Chain></li> + <li>select ARCH_VERSTAGE_<Tool Chain></li> + </ul> + </li> + <li>Makefile.inc - Specify the include paths</li> + <li>memmap.c - Top of usable RAM</li> +</ul> + + +<hr> +<h1><a name="Descriptor">Start Booting</a></h1> +<p> + Some SoC parts require additional firmware components in the flash. + This section describes how to add those pieces. +</p> + +<h2>Intel Firmware Descriptor</h2> +<p> + The Intel Firmware Descriptor (IFD) is located at the base of the flash part. + The following command overwrites the base of the flash image with the Intel + Firmware Descriptor: +</p> +<pre><code>dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1</code></pre> + + +<h2><a name="MEB">Management Engine Binary</a></h2> +<p> + Some SoC parts contain and require that the Management Engine (ME) be running + before it is possible to bring the x86 processor out of reset. A binary file + containing the management engine code must be added to the firmware using the + ifdtool. The following commands add this binary blob: +</p> +<pre><code>util/ifdtool/ifdtool -i ME:me.bin build/coreboot.rom +mv build/coreboot.rom.new build/coreboot.rom +</code></pre> + + +<h2><a name="EarlyDebug">Early Debug</a></h2> +<p> + Early debugging between the reset vector and the time the serial port is enabled + is most easily done by writing values to port 0x80. +</p> + + +<h2>Success</h2> +<p> + When the reset vector is successfully invoked, port 0x80 will output the following value: +</p> +<ul> + <li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a> + - Bootblock successfully executed the + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a> + and entered the 16-bit code at + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a> + </li> +</ul> + + +<hr> +<p>Modified: 31 January 2016</p> + </body> +</html>
\ No newline at end of file diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html new file mode 100644 index 0000000000..1dbef9cbda --- /dev/null +++ b/Documentation/Intel/development.html @@ -0,0 +1,78 @@ +<!DOCTYPE html> +<html> + <head> + <title>Development</title> + </head> + <body> + +<h1>Intel® x86 Coreboot/FSP Development Process</h1> +<p> + The x86 development process for coreboot is broken into the following components: +</p> +<ul> + <li>Coreboot <a target="_blank" href="SoC/soc.html">SoC</a> development</li> + <li>Coreboot <a target="_blank" href="Board/board.html">mainboard</a> development</li> + <li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration</li> +</ul> +<p> + The development process has two main phases: +</p> +<ol> + <li>Minimal coreboot; This phase is single threaded</li> + <li>Adding coreboot features</li> +</ol> + +<h2>Minimal Coreboot</h2> +<p> + The combined steps below describe how to bring up a minimal coreboot for a + system-on-a-chip (SoC) and a development board: +</p> +<table> + <tr bgcolor="#ffffc0"> + <td>The initial coreboot steps are single threaded! + The initial minimal FSP development is also single threaded. + Progress can speed up by adding more developers after the minimal coreboot/FSP + implementation reaches the payload. + </td> + </tr> +</table> +<ol> + <li>Get the necessary tools: + <ul> + <li>Linux: Use your package manager to install m4 bison flex and the libcurses development + package. + <ul> + <li>Ubuntu or other Linux distribution that use apt, run: +<pre><code>sudo apt-get install m4 bison flex libncurses5-dev +</code></pre> + </li> + </ul> + </li> + </ul> + </li> + <li>Build the cross tools for i386: + <ul> + <li>Linux: +<pre><code>make crossgcc-i386</code></pre> + To use multiple processors for the toolchain build (which takes a long time), use: +<pre><code>make crossgcc-i386 CPUS=N</code></pre> + where N is the number of cores to use for the build. + </li> + </ul> + </li> + <li>Get something to build: + <ol type="A"> + <li><a target="_blank" href="fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li> + <li><a target="_blank" href="SoC/soc.html#RequiredFiles">SoC</a> required files</li> + <li><a target="_blank" href="Board/board.html#RequiredFiles">Board</a> required files</li> + </ol> + </li> + <li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li> + <li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li> +</ol> + + +<hr> +<p>Modified: 31 January 2016</p> + </body> +</html>
\ No newline at end of file diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html new file mode 100644 index 0000000000..c210ffb89c --- /dev/null +++ b/Documentation/Intel/fsp1_1.html @@ -0,0 +1,50 @@ +<!DOCTYPE html> +<html> + <head> + <title>FSP 1.1</title> + </head> + <body> + +<h1>x86 FSP 1.1 Development</h1> +<p> + Firmware Support Package (FSP) development requires System-on-a-Chip (SoC) + and board support. The combined steps are listed + <a target="_blank" href="x86Development.html">here</a>. + The development steps for FSP are listed below: +</p> +<ol> + <li><a href="#RequiredFiles">Required Files</a></li> +</ol> + +<p> + FSP Documentation: +</p> +<ul> + <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li> +</ul> + +<hr> +<h1><a name="RequiredFiles">Required Files</a></h1> +<h2><a name="CorebootRequiredFiles">Coreboot Required Files</a></h2> +<ol> + <li>Create the following directories if they do not already exist: + <ul> + <li>src/vendorcode/intel/fsp/fsp1_1/<Chip Family></li> + <li>3rdparty/blobs/mainboard/<Board Vendor>/<Board Name></li> + </ul> + </li> + <li> + The following files may need to be copied from the FSP build or release into the + directories above if they are not present or are out of date: + <ul> + <li>FspUpdVpd.h: src/vendorcode/intel/fsp/fsp1_1/<Chip Family>/FspUpdVpd.h</li> + <li>FSP.bin: 3rdparty/blobs/mainboard/<Board Vendor>/<Board Name>/fsp.bin</li> + </ul> + </li> +</ol> + + +<hr> +<p>Modified: 31 January 2016</p> + </body> +</html>
\ No newline at end of file diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html new file mode 100644 index 0000000000..6d5810f110 --- /dev/null +++ b/Documentation/Intel/index.html @@ -0,0 +1,42 @@ +<!DOCTYPE html> +<html> + <head> + <title>Intel® x86</title> + </head> + <body> + +<h1>Intel® x86 Boards</h1> +<ul> + <li><a target="_blank" href="Board/galileo.html">Galileo</a></li> +</ul> + + + +<h1>Intel® x86 SoCs</h1> +<ul> + <li><a target="_blank" href="SoC/quark.html">Quark™</a></li> +</ul> + + + +<h1>x86 Coreboot Development</h1> +<ul> + <li><a target="_blank" href="development.html">Overall</a> development</li> + <li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration + </li> + <li><a target="_blank" href="SoC/soc.html">SoC</a> support</li> + <li><a target="_blank" href="Board/board.html">Board</a> support</li> +</ul> + +<h1>Documentation</h1> +<ul> + <li>Get the <a target="_blank" href="https://www.coreboot.org/Git">coreboot source</li> + <li>Intel® 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf">Software Developer Manual</a></li> + <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li> +</ul> + + +<hr> +<p>Modified: 31 January 2016</p> + </body> +</html>
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