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authorPhilipp Hug <philipp@hug.cx>2018-07-07 15:54:37 +0200
committerRonald G. Minnich <rminnich@gmail.com>2018-09-14 14:33:09 +0000
commit2326a284ac6a6646a918331425952ece2da723c1 (patch)
treed83f6fc80597a33132895edd356171547c753343 /Documentation
parent2912e8e5dc66708703db79df87e3215408a653ae (diff)
downloadcoreboot-2326a284ac6a6646a918331425952ece2da723c1.tar.xz
riscv: add trampoline in MBR block to support boot mode 1
Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock. Tested on hardware: boot mode 15: works as before boot mode 1: jump to bootblock works, but bootblock needs to be modified to move the stack to L2LIM. This will be in a separate commit. Further changes are needed in the bootblock Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/mainboard/sifive/hifive-unleashed.md2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md
index c5c015ddc1..1d07cb7df6 100644
--- a/Documentation/mainboard/sifive/hifive-unleashed.md
+++ b/Documentation/mainboard/sifive/hifive-unleashed.md
@@ -11,7 +11,7 @@ For general setup instructions, please refer to the [Getting Started Guide].
The following things are still missing from this coreboot port:
-- Trampoline in the MBR block to support boot mode 1
+- Support running romstage from flash (fix stack) to support boot mode 1
- CBMEM support
- FU540 clock configuration
- FU540 RAM init