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| author | Duncan Laurie <dlaurie@google.com> | 2020-10-10 00:18:08 +0000 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2020-11-20 00:24:53 +0000 |
| commit | e997d85e3be50cda1ffdcf4d76014b713fe4951b (patch) | |
| tree | 43fc12b32f3a151c8e58f82b29c6928fb7adda2f /MAINTAINERS | |
| parent | 64bc26ad1553eec6bbbd6deac21a3e79ca7ce455 (diff) | |
| download | coreboot-e997d85e3be50cda1ffdcf4d76014b713fe4951b.tar.xz | |
soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox
This SOC overrides the common PMC device and instantiates the PMC device
in the SSDT. It needs to call the common PMC function to provide the
IPC mailbox method.
The common PCIe RTD3 driver can also be enabled which will allow
mainboards to enable Runtime D3 power control for PCIe devices.
BUG=b:160996445
TEST=boot on volteer with this driver enabled for the NVMe device in the
devicetree and disassemble the SSDT to ensure the RTD3 code is present.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ifa54ec3b8cebcc2752916cc4f8616fcb6fd2fecc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'MAINTAINERS')
0 files changed, 0 insertions, 0 deletions