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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-25 02:31:48 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-06 18:15:27 +0000 |
| commit | 0b75679cbb9302e16ff4cb2266879cfb5476a4a2 (patch) | |
| tree | 6a5034476e714d59902937fc14fbf99f02435e9f /Makefile.inc | |
| parent | eaf83489f619ec974943c53b006f17042e3b7b9e (diff) | |
| download | coreboot-0b75679cbb9302e16ff4cb2266879cfb5476a4a2.tar.xz | |
Makefile.inc: Optimize generating the default x86 fmap
Put the FMAP FMAP region right above the coreboot CBFS region.
The other regions like RW_MRC_CACHE and CONSOLE often have alignment
requirements so it makes sense to put those on top. This also
simplifies the code the generate the default fmap a little.
Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30419
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Makefile.inc')
| -rw-r--r-- | Makefile.inc | 26 |
1 files changed, 11 insertions, 15 deletions
diff --git a/Makefile.inc b/Makefile.inc index 7d6bc7ce47..3ec1e638a9 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -852,19 +852,16 @@ FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)) FMAP_BIOS_SIZE := $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f) # position and size of flashmap, relative to BIOS_BASE -FMAP_FMAP_BASE := 0 -FMAP_FMAP_SIZE := 0x200 # # X86 CONSOLE FMAP region # # position, size and entry line of CONSOLE relative to BIOS_BASE, if enabled +FMAP_CONSOLE_BASE := 0 ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) -FMAP_CONSOLE_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) FMAP_CONSOLE_SIZE := $(CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE) FMAP_CONSOLE_ENTRY := CONSOLE@$(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE) else # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) -FMAP_CONSOLE_BASE := 0 FMAP_CONSOLE_SIZE := 0 FMAP_CONSOLE_ENTRY := endif # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) @@ -874,13 +871,8 @@ endif # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) # # position, size and entry line of MRC_CACHE relative to BIOS_BASE, if enabled ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) -ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) -FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ +FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ $(FMAP_CONSOLE_SIZE)), 0x10000) -else -FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_FMAP_BASE) \ - $(FMAP_FMAP_SIZE)), 0x10000) -endif FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE) FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE) else # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) @@ -890,14 +882,18 @@ FMAP_MRC_CACHE_ENTRY := endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) # +# X86 FMAP region +# +# +# position, size +FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE)) +FMAP_FMAP_SIZE := 0x200 + +# # X86 COREBOOT default cbfs FMAP region # # position and size of CBFS, relative to BIOS_BASE -ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) -FMAP_CBFS_BASE := $(call int-add, $(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE)) -else -FMAP_CBFS_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_FMAP_SIZE)) -endif +FMAP_CBFS_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) else # ifeq ($(CONFIG_ARCH_X86),y) DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd |