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author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2018-06-04 23:02:46 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2018-06-26 05:59:52 +0000 |
commit | c1072f2fc73926bbe73b507dda2e9346d39e041f (patch) | |
tree | 811ab96f0d55d6c0d8fb1d942c4d446cdacfad9d /Makefile | |
parent | 1dc188fad0c6c209a0185bae6b53d5798e7cf043 (diff) | |
download | coreboot-c1072f2fc73926bbe73b507dda2e9346d39e041f.tar.xz |
cbfstool: Update FIT entries in the second bootblock
Once a second bootblock has been added using topswap (-j)
option, Update the entries in second FIT using -j option with
update-fit command.
Additionally add a -q option which allows to insert the address of
a FMAP region (which should hold a microcode) as the first entry in
the second FIT.
BUG=None
BRANCH=None
TEST= Create ROM images with -j options and update FIT using -q option.
example:
./build/util/cbfstool/cbfstool coreboot.tmp create \
-M build/fmap.fmap -r COREBOOT,FW_MAIN_A,FW_MAIN_B,RW_LEGACY
build/util/cbfstool/cbfstool coreboot.tmp add \
-f build/cbfs/fallback/bootblock.bin -n bootblock -t \
bootblock -b -49152 -j 0x10000
build/util/cbfstool/cbfstool coreboot.tmp add-master-header -j 0x10000
build/util/cbfstool/cbfstool coreboot.tmp add -f build/cpu_microcode_blob.bin \
-n cpu_microcode_blob.bin -t microcode -r COREBOOT -a 16
build/util/cbfstool/cbfstool coreboot.tmp. update-fit \
-n cpu_microcode_blob.bin -x 4 -j 0x10000 -q FW_MAIN_A
Also try the failure scenarion by providing invalid topswap size.
Change-Id: I9a417031c279038903cdf1761a791f2da0fe8644
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/26836
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Makefile')
0 files changed, 0 insertions, 0 deletions