soc/intel/tigerlake: Enable FSP-S compression

Use LZ4 compression technique to compress FSP-S. This provides some
SPI ROM space savings (~36 KiB) in each CBFS. FSP-M is XIP and hence not
compressed. LZ4 is chosen over LZMA since the decompression saves
~25 ms for an extra overhead of ~1KiB.

LZ4 Compression:
fsps.bin	0xe6fc0	fsp	254262 LZ4  (290816 decompressed)
LZ4 Decompression:
 17:starting LZ4 decompress (ignore for x86)          712,361 (1,072)
 18:finished LZ4 decompress (ignore for x86)          750,695 (38,334)

LZMA Compression:
fsps.bin	0xe6fc0	fsp	253415 LZMA (290816 decompressed)
LZMA Decompression:
 15:starting LZMA decompress (ignore for x86)         707,696 (1,150)
 16:finished LZMA decompress (ignore for x86)         767,763 (60,067)

BUG=b:158034451
TEST=Build and boot volteer mainboard.

Change-Id: I91e33eb7b688b5383f3a0075a28ac21250314973
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42444
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

0 files changed, 0 insertions, 0 deletions