mb/intel/jasperlake_rvp: Add initial mainboard code

This is a initial mainboard code aimed to serve as base for
further mainboard check-ins.

This is a copy patch from icelake_rvp as on commit ID:
I64db2460115f5fb35ca197b83440f8ee47470761

Below are the changes done over the copy patch:

 1. Rename "Icelake" with "Jasperlake".
 2. Replace "icelake_rvp" with "jasperlake_rvp".
 3. Rename "icl" with "jsl".
 4. Remove unwanted SPD file, add empty SPD as
    placeholder.
 5. Replace "soc/intel/icelake" with "soc/intel/tigerlake"
    as tigerlake SOC hosts jasperlake code as well.
 6. Empty romstage_fsp_params.c, to fill it later with
    SOC specific config.
 7. Empty GPIO configuration, to be filled as per board.
 8. Change copyright year to 2019.
 9. Add two board support namely BOARD_INTEL_JASPERLAKE_RVP
    and BOARD_INTEL_JASPERLAKE_RVP_EXT_EC
 10. Replace icl_u and icl_y variant with jslrvp variant.
 11. Remove basebord gpio.c and rely on variant override.
 12. Remove HDA verb table and config support.

Changes to follow on top of this:
 1. Add correct memory parameters, add SPDs.
 2. Clean up devicetree as per jasperlake SOC.
 3. Add GPIO support.
 4. Update chromeos.fmd to make 10MB BIOS region.

TEST=Build jasperlake rvp board

Change-Id: I3314215807959b7348b71933fbba98e6487c0632
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>

0 files changed, 0 insertions, 0 deletions