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author | Lijian Zhao <lijian.zhao@intel.com> | 2017-05-04 13:27:09 -0700 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2017-05-12 20:19:40 +0200 |
commit | 55cad16ca5261179aa95726ee8e7f6610ba92913 (patch) | |
tree | 72f70eb29f53a5978ae1e27dc571705b5222cb56 /Makefile | |
parent | 4becfcdafc2a9c6220140c3c603f8efdac1cbdd7 (diff) | |
download | coreboot-55cad16ca5261179aa95726ee8e7f6610ba92913.tar.xz |
mainboard/google/reef: Config needed GPIO for pull-up WA
This change is needed to minimize circuit level stress, by adjusting
circuit voltage for proper operation.
For mem config GPIO changes:
To avoid leakge as those pins have internal 20K pull and 3.3K pull down
on mainboard, change internal pull up to none.
BUG=b:37998248
TEST=Boot up into OS and enter s0ix.
Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/19577
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Makefile')
0 files changed, 0 insertions, 0 deletions