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author | Marc Jones <marc.jones@amd.com> | 2007-12-19 01:52:11 +0000 |
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committer | Marc Jones <marc.jones@amd.com> | 2007-12-19 01:52:11 +0000 |
commit | ba8965c0395a295828911cb375e7122051e73962 (patch) | |
tree | ea593e7a7d743cd6bd80c246379b8fafeaea9079 /NEWS | |
parent | 2ce8bfd251cfee8a19c09217ace28a5be2684311 (diff) | |
download | coreboot-ba8965c0395a295828911cb375e7122051e73962.tar.xz |
Changed the stop_this_cpu() to just hlt.
Removed local APIC INIT (don't worry the APIC and AP are still initialized).
The local APIC INIT seemed to be the incorrect thing to do to stop an AP.
The Intel Multiprocessor specification indicated that a vector should be set
and a START should happen following an INIT. Then AP will execute the
instructions pointed to by the vector. There is no vector or start in
stop_this_cpu(). This seems to put the AP in an in-between state. In the case
of Barcelona the AP's MSRs and PCI register are not accessible by the hardware
debugger.
The better solution seems to be to just put the AP in a hlt and allow the AP
to go into C1. Then APIC managing software running on the BSP can program the
AP as needed.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'NEWS')
0 files changed, 0 insertions, 0 deletions