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authorUwe Hermann <uwe@hermann-uwe.de>2010-09-19 21:12:05 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-09-19 21:12:05 +0000
commit0865b4d9c06d584cfb43793f710d7dfa58e3275e (patch)
treef00c68b85d4a9ba86f46affb7f817b4604808a29 /README
parent78301d02b01d01302e6f9ce95db1e59c360a0ba9 (diff)
downloadcoreboot-0865b4d9c06d584cfb43793f710d7dfa58e3275e.tar.xz
Make ASUS P3B-F RAM init actually work by enabling SPD access.
On this board all reads from SPD return 0xff by default, there's a custom GPIO fiddling needed to enable access to the SPD SMBus offsets at 0x50-0x53. While coreboot actually sort of booted sometimes before r5193, that was just sheer luck as the RAM init was hardcoded in certain ways. Since the proper, more heavily SPD-based RAM init the brokenness of the ASUS P3B-F RAM init was becoming visible. This patch uses GPIOs to enable access to the SPD SMBus offsets, and resets the GPIOs again after RAM init (this is needed to allow for lm-sensors to work, for example). Tested successfully on hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Idwer Vollering <vidwer@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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