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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-06-05 18:41:00 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-06-11 19:22:42 +0200 |
| commit | 2030d257d19920904ad370509404145c18627fac (patch) | |
| tree | 7c6b095d0439b7e42fce52d7759c08bf6692cda1 /README | |
| parent | db601b68182df47a28b106ba07e97f222ff39140 (diff) | |
| download | coreboot-2030d257d19920904ad370509404145c18627fac.tar.xz | |
arch/x86: Support "weak" BIST and timestamp save routines
Not all x86 architectures support the mm register set. The default
routine that saves BIST in mm0 and a "weak" routine that saves the TSC
value in mm2:mm1. Select the Kconfig value
BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP to provide a replacement routine to
save the BIST and timestamp values.
TEST=Build and run on Amenia and Galileo Gen2.
Change-Id: I8119e74664ac3522c011767d424d441cd62545ce
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15126
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'README')
0 files changed, 0 insertions, 0 deletions