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| author | Xavi Drudis Ferran <xdrudis@tinet.cat> | 2011-02-27 23:45:34 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2011-02-27 23:45:34 +0000 |
| commit | a5cbd25e48b5e33726ff7f7a193b10622207fd22 (patch) | |
| tree | de3620b2fedb111afd7c82bc8d84168959523404 /README | |
| parent | d7294596218addf11feefb4cb2411eb7729b5b11 (diff) | |
| download | coreboot-a5cbd25e48b5e33726ff7f7a193b10622207fd22.tar.xz | |
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).
No change of behaviour intended.
Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We now take apart F3xD4,
Clock Power/Timing Control 0 to its own function.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'README')
0 files changed, 0 insertions, 0 deletions