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authorPhilipp Deppenwiese <zaolin@das-labor.org>2017-01-18 00:12:38 +0100
committerMartin Roth <martinroth@google.com>2017-01-18 17:46:23 +0100
commit96326d3aefa0cfe252b44c68b540653ec47e9aa9 (patch)
tree2ed8c212d4330f0205db2c29179b135fc3adfa07 /configs/builder/config.lenovo_t420
parent607796a4ff169f375e63853713cfeef0a89a0b2c (diff)
downloadcoreboot-96326d3aefa0cfe252b44c68b540653ec47e9aa9.tar.xz
configs/builder: Add Sandy/Ivy Bridge Thinkpad configurations
The coreboot builder makes use of the pre defined configuration files by executing abuild with -d option. These configuration files contain a basic configuration. Change-Id: I41470fe7aaa0fdae545ad9d702326a202d0d2312 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/18161 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'configs/builder/config.lenovo_t420')
-rw-r--r--configs/builder/config.lenovo_t42019
1 files changed, 19 insertions, 0 deletions
diff --git a/configs/builder/config.lenovo_t420 b/configs/builder/config.lenovo_t420
new file mode 100644
index 0000000000..bb653b353c
--- /dev/null
+++ b/configs/builder/config.lenovo_t420
@@ -0,0 +1,19 @@
+CONFIG_USE_OPTION_TABLE=y
+CONFIG_USE_BLOBS=y
+CONFIG_VENDOR_LENOVO=y
+CONFIG_VGA_BIOS=y
+CONFIG_VGA_BIOS_FILE="site-local/pci8086,0126.rom"
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_HAVE_ME_BIN=y
+CONFIG_DRIVERS_PS2_KEYBOARD=y
+CONFIG_IFD_BIN_PATH="site-local/descriptor.bin"
+CONFIG_ME_BIN_PATH="site-local/me.bin"
+CONFIG_HAVE_GBE_BIN=y
+CONFIG_BOARD_LENOVO_T420=y
+CONFIG_NO_POST=y
+CONFIG_GBE_BIN_PATH="site-local/gbe.bin"
+CONFIG_PCIEXP_CLK_PM=y
+CONFIG_PCIEXP_L1_SUB_STATE=y
+CONFIG_LPC_TPM=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000
+CONFIG_PAYLOAD_NONE=y