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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-18 19:40:48 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-19 19:31:08 +0000
commit4f14cd8a39e65811af08296633842289efa42927 (patch)
tree1cece9915f897af008d2d83701088b3054c4ab93 /configs/config.google_reef_cros
parent6766f4fd046604e6376c9769cd5f8357dec6a80a (diff)
downloadcoreboot-4f14cd8a39e65811af08296633842289efa42927.tar.xz
arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE
If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory. This also adds board reset for failing to load postcar from stage cache. Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'configs/config.google_reef_cros')
-rw-r--r--configs/config.google_reef_cros1
1 files changed, 0 insertions, 1 deletions
diff --git a/configs/config.google_reef_cros b/configs/config.google_reef_cros
index 82b9b5234e..9bbb3b3f59 100644
--- a/configs/config.google_reef_cros
+++ b/configs/config.google_reef_cros
@@ -3,7 +3,6 @@ CONFIG_VENDOR_GOOGLE=y
CONFIG_BOARD_GOOGLE_REEF=y
CONFIG_CHROMEOS=y
CONFIG_ADD_FSP_BINARIES=y
-CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y
CONFIG_ELOG_GSMI=y
CONFIG_ELOG_BOOT_COUNT=y
CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144