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authorPatrick Georgi <pgeorgi@google.com>2018-10-22 14:54:48 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-23 07:11:31 +0000
commite7864ceabc2a5b808007688b2b6fb437a154b29a (patch)
treeb198c99eca3fd82a2c6662e952cb5a7431c64b8c /configs/config.google_reef_cros
parent88030b722dfa31291aa263ff54e4d59431d4557b (diff)
downloadcoreboot-e7864ceabc2a5b808007688b2b6fb437a154b29a.tar.xz
soc/intel/apollolake: Add reset code to postcar stage
Also add a test case for that, a config taken from chromiumos with some references to binaries dropped that aren't in our blobs repo (eg audio firmware). Change-Id: I411c0bacefd9345326f26db4909921dddba28237 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/29223 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'configs/config.google_reef_cros')
-rw-r--r--configs/config.google_reef_cros15
1 files changed, 15 insertions, 0 deletions
diff --git a/configs/config.google_reef_cros b/configs/config.google_reef_cros
new file mode 100644
index 0000000000..82b9b5234e
--- /dev/null
+++ b/configs/config.google_reef_cros
@@ -0,0 +1,15 @@
+CONFIG_USE_BLOBS=y
+CONFIG_VENDOR_GOOGLE=y
+CONFIG_BOARD_GOOGLE_REEF=y
+CONFIG_CHROMEOS=y
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y
+CONFIG_ELOG_GSMI=y
+CONFIG_ELOG_BOOT_COUNT=y
+CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144
+CONFIG_SPI_FLASH_SMM=y
+# CONFIG_CONSOLE_SERIAL is not set
+CONFIG_CMOS_POST=y
+CONFIG_CMOS_POST_OFFSET=0x70
+CONFIG_CMOS_POST_EXTRA=y
+CONFIG_PAYLOAD_NONE=y