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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-10-30 14:52:01 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-11-08 21:59:14 +0000 |
| commit | 07132a4c3202de9f5affe10d90f481b9bd41afc7 (patch) | |
| tree | 0fb5bf7eda1404b73b6899cc044a177fde9661a2 /configs/config.intel_galileo_gen2.debug | |
| parent | 5f0520a90951eba302973025b8e531cb915152dd (diff) | |
| download | coreboot-07132a4c3202de9f5affe10d90f481b9bd41afc7.tar.xz | |
amd/stoneyridge: Add PSP definitions southbridge and iomap
Define the PSP's BAR3 and BAR3 enable bit. Define a default base
address for BAR3.
Change-Id: I59a0ec59b7c6bbc6468b3096ec8d025832349f44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'configs/config.intel_galileo_gen2.debug')
0 files changed, 0 insertions, 0 deletions