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| author | Subrata Banik <subrata.banik@intel.com> | 2019-12-19 14:45:52 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-26 10:43:42 +0000 |
| commit | f96c638a60fdca149a716e773749c20bd4080ee3 (patch) | |
| tree | 0a39d2b44bf2654038305acccebd3e7bb83a5f7c /configs/config.pcengines_apu3 | |
| parent | f814ff15f977bbb409d944dfad687573ac3672b2 (diff) | |
| download | coreboot-f96c638a60fdca149a716e773749c20bd4080ee3.tar.xz | |
vendorcode/intel/fsp/fsp2_0/tgl: Add FSP header files for Tiger Lake
Add header files for FSP for Tiger Lake platform version 2457.
Change-Id: I52bb2e164cc89d3535fe67493686d1e8e064e31e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'configs/config.pcengines_apu3')
0 files changed, 0 insertions, 0 deletions