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| author | Nick Vaccaro <nvaccaro@google.com> | 2020-08-25 11:14:17 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-08-28 05:01:40 +0000 |
| commit | c5428a990a0dd30a0a8eea28475dd8e5cdec7d72 (patch) | |
| tree | 43430fb282cfdd439ef086de3738f3bdb821015b /configs/config.pcengines_apu5 | |
| parent | 0245f43bcd829e6352cb74206ab8ae30b8f3a21f (diff) | |
| download | coreboot-c5428a990a0dd30a0a8eea28475dd8e5cdec7d72.tar.xz | |
mb/google/volteer: update Delbin SPD for H9HCNNNCPMMLXR-NEE
I noticed that re-running the lpddr4x SPD parts id tool that generates
the variants/VARIANT_NAME/memory/Makefile.inc changed the SPD that is
used for the H9HCNNNCPMMLXR-NEE part.
$ go run ./util/spd_tools/lp4x/gen_part_id.go \
src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/delbin/memory
src/mainboard/google/volteer/variants/delbin/memory/mem_list_variant.txt
Based on the currently checked in generic SPDs for LPDDR4x, this
operation changes the Makefile.inc to use lp4x-spd-3.hex for the
H9HCNNNCPMMLXR-NEE part instead of lp4x-spd-2.hex.
This change updates that discrepancy in Delbin's memory Makefile.inc.
BUG=none
TEST=none
Change-Id: I9a19ab7b1bcdc3814fdd9c462ca2f590c8ed2935
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44785
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'configs/config.pcengines_apu5')
0 files changed, 0 insertions, 0 deletions