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| author | Subrata Banik <subrata.banik@intel.com> | 2019-11-01 15:44:17 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-11-04 08:20:28 +0000 |
| commit | 14d59912f8cdbec7e0121042c43e5728dc361509 (patch) | |
| tree | d573786008c760b20004b22460ab07aae5a188af /configs/config.pcengines_apu5 | |
| parent | 645f244fd08b463b93c50c9d71e3767e1c9ef91a (diff) | |
| download | coreboot-14d59912f8cdbec7e0121042c43e5728dc361509.tar.xz | |
soc/intel/icelake: Add alignment check for TSEG base and size
This patch ensures to not set SMRR if TSEG base is not align with TSEG size
Change-Id: I77d1cb2fd287f45859cde37a564ea7c147d5633f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36542
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'configs/config.pcengines_apu5')
0 files changed, 0 insertions, 0 deletions