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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-09-01 16:10:06 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-08 05:25:14 +0000 |
| commit | 4cba419676de40c76e4979957baf6039da8b8bf5 (patch) | |
| tree | 84b609f95f50e1022005022fa4639b501e8a1fe7 /configs | |
| parent | 62669a24eaf5236a60eebf8e26eefc984ca321ee (diff) | |
| download | coreboot-4cba419676de40c76e4979957baf6039da8b8bf5.tar.xz | |
soc/intel/common: Add SMRR Lock Supported bit definition for MTRR_CAP
The IA32_MTRR_CAP register has a bit which indicates that the SMRR MSRs
can be "locked" and this patch adds the definition for that.
BUG=b:164489598
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1254fb40c790f2a83dd11c2aabcf9bdf922b9395
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'configs')
0 files changed, 0 insertions, 0 deletions