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| author | Duncan Laurie <dlaurie@chromium.org> | 2012-10-08 15:26:54 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-12 04:23:30 +0100 |
| commit | 2a700ec16322561ad487e6ef1ae8878f9a7e4357 (patch) | |
| tree | 97edc0be8718f9cf7877a02ebf1c0e27e1626d16 /documentation/POSTCODES | |
| parent | 924342bb2b9e429d66a693503c9f944655da4bb8 (diff) | |
| download | coreboot-2a700ec16322561ad487e6ef1ae8878f9a7e4357.tar.xz | |
SPI: Configure Software Sequence SPI Freq to match descriptor
Right now the SPI bus is getting set to 20mhz for transactions
initiated with the software sequence interface.
In order to be able to do reasonable fastread/write/erase we
can bump this up to a higher value at boot before it gets
locked at 20mhz.
To do this read out the speed set in the SPI descriptor for
hardware sequencing and apply it to software sequencing.
Change-Id: I79aa2fe7f30f734785d61955ed81329fc654f4a4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'documentation/POSTCODES')
0 files changed, 0 insertions, 0 deletions