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authorMike Loptien <mike.loptien@se-eng.com>2013-03-15 11:11:12 -0600
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-03-17 19:55:59 +0100
commit594ea4ac5fef354dda573b3b3670fe946ce65cd9 (patch)
tree32c42d94f5bd2deb07dd2d24731e7cebdd66d2ba /documentation/codeflow.svg
parent8c72670ba5c4283b2a1a2513f47f40b949094648 (diff)
downloadcoreboot-594ea4ac5fef354dda573b3b3670fe946ce65cd9.tar.xz
ASROCK Fam14 DSDT: Add secondary bus range to PCI0
Adding the 'WordBusNumber' macro to the PCI0 CRES ResourceTemplate in the Persimmon DSDT. This sets up the bus number for the PCI0 device and the secondary bus number in the CRS method. This change came in response to a 'dmesg' error which states: '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS' By adding the 'WordBusNumber' macro, ACPI can set up a valid range for the PCIe downstream busses, thereby relieving the Linux kernel from "guessing" the valid range based off _BBN or assuming [0-0xFF]. The Linux kernel code that checks this bus range is in `drivers/acpi/pci_root.c`. PCI busses can have up to 256 secondary busses connected to them via a PCI-PCI bridge. However, these busses do not have to be sequentially numbered, so leaving out a section of the range (eg. allowing [0-0x7F]) will unnecessarily restrict the downstream busses. This is the same change as made to Persimmon with change-id I44f22: http://review.coreboot.org/#/c/2592/ Change-Id: I5184df8deb7b5d2e15404d689c16c00493eb01aa Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2736 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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