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| author | Lin Huang <hl@rock-chips.com> | 2016-09-15 22:59:55 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-11-02 17:29:48 +0100 |
| commit | 883f5cbdcea6e8e4dbca57ff0a430338c9159ed2 (patch) | |
| tree | 5fb86a9b3dcc8537c240c81ebafd275897fe9948 /payloads/coreinfo/coreinfo.c | |
| parent | 84164603188175abd2a3d8eeab1adc5efc33330f (diff) | |
| download | coreboot-883f5cbdcea6e8e4dbca57ff0a430338c9159ed2.tar.xz | |
rockchip/rk3399: sdram: also prepare the index1 configuration
To enable DDR Dynamic Voltage and Frequency Scaling (DVFS) we need to
train alternative configurations first, so do the training and store the
values.
BUG=None
BRANCH=None
TEST=Boot from kevin
Change-Id: I944a4b297a4ed6966893aa09553da88171307a42
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 94533ff3ba21bcb0ace00bedcf0cebb89a341be2
Original-Change-Id: I4a98bc0db5553d154fedb657e35b926a92aa80c7
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/386596
Original-Commit-Ready: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17104
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'payloads/coreinfo/coreinfo.c')
0 files changed, 0 insertions, 0 deletions