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| author | Cheng-Yi Chiang <cychiang@chromium.org> | 2017-11-01 15:01:34 +0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-11-14 21:21:48 +0000 |
| commit | 09ab15798a232d70824e60699f4c7c296234f82f (patch) | |
| tree | 2a75ef337c0ba27f023ae589b81196a9bf7a47b9 /payloads/coreinfo/pci_module.c | |
| parent | 37da8846faa6d83c12a7f76b9c451a72805850bc (diff) | |
| download | coreboot-09ab15798a232d70824e60699f4c7c296234f82f.tar.xz | |
mb/google/eve: Add DSP calibration clock name/rate for RT5514
Add a property for DSP calibration clock name and rate such that
RT5514 codec driver can control ssp1_mclk for DSP clock calibration.
BUG=b:67763576
TEST=boot on eve check RT5514 codec driver can get this device
property.
Change-Id: Icf9695ef67efb2bb073e39b2ece02d57f0460a0c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Original-Change-Id: Ie204dda81a099f23beb20be71380a8494a9bee31
Original-Reviewed-on: https://chromium-review.googlesource.com/756261
Original-Reviewed-by: Dylan Reid <dgreid@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/22451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'payloads/coreinfo/pci_module.c')
0 files changed, 0 insertions, 0 deletions