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authorMartin Roth <martin.roth@se-eng.com>2014-07-25 14:39:05 -0600
committerMartin Roth <gaumless@gmail.com>2014-09-12 23:16:29 +0200
commit4d7d25f38abac4bcd3ea88a50b5f529f1e9ddb44 (patch)
tree51c2447343e840d5b24008d07f2ad231a20f2c9e /payloads/external/SeaBIOS
parentb3997ba6f2ba26e0dfa851caed98f030ac25ffd0 (diff)
downloadcoreboot-4d7d25f38abac4bcd3ea88a50b5f529f1e9ddb44.tar.xz
payloads/external/SeaBIOS: Allow setting buffers below 0xC0000
Add the option to coreboot to set the SeaBIOS buffers below 0xC0000. This is a requirement on the Intel Rangeley processor because it is designed so that only the processor can write the higher memory areas. This prevents USB and SATA from bus-mastering into the buffers when they're set in the typical 0xE0000 area. This will be set to Y unless defaulted to N by the mainboard or chipset. Push the SeaBIOS buffers down to 0x90000 segment for Mohon Peak Change-Id: I15638605d1c66a2277d4b852796db89978551a34 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6364 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'payloads/external/SeaBIOS')
-rw-r--r--payloads/external/SeaBIOS/Makefile.inc3
1 files changed, 3 insertions, 0 deletions
diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc
index 97f9d5674d..21bc9a70e8 100644
--- a/payloads/external/SeaBIOS/Makefile.inc
+++ b/payloads/external/SeaBIOS/Makefile.inc
@@ -31,6 +31,9 @@ ifeq ($(CONFIG_CONSOLE_SERIAL),y)
else
echo "# CONFIG_DEBUG_SERIAL is not set" >> seabios/.config
endif
+ifneq ($(CONFIG_SEABIOS_MALLOC_UPPERMEMORY),y)
+ echo "# CONFIG_MALLOC_UPPERMEMORY is not set" >> $(OUT)/seabios/.config
+endif
ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y)
echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config
endif