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author | Nico Huber <nico.huber@secunet.com> | 2019-06-28 16:12:47 +0200 |
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committer | Nico Huber <nico.h@gmx.de> | 2019-07-13 12:47:48 +0000 |
commit | 8417485f95b07aa76d81d7006fa5097d018d6df2 (patch) | |
tree | 7c01f6e45a2ec6cf07c7a3b30c2499ef85487dba /payloads/external/tianocore/Makefile | |
parent | 0c4ed4bd7edf3c0a131af717eb6dc8aeec44b47e (diff) | |
download | coreboot-8417485f95b07aa76d81d7006fa5097d018d6df2.tar.xz |
soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSP
We got rid of the dangerous reconfiguration of arbitrary pads in
coreboot, but FSP still overrode that. Make sure that it doesn't
enable a UART for debug output when it isn't configured in core-
boot.
This, again, shows how dangerous it is to leave any FSP UPD at
its binary default.
Change-Id: I7280a80f71ddddbe78352eb696e6f5844d2df0b2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'payloads/external/tianocore/Makefile')
0 files changed, 0 insertions, 0 deletions