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authorWonkyu Kim <wonkyu.kim@intel.com>2020-01-28 19:53:01 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-02-05 09:32:42 +0000
commit3f5f74d1349625fa33bcbdfd2956d1e36b3f236d (patch)
treef2be2a33e6ea6a8116384c5ff9102c187d9b027c /payloads/external
parentcf2ac543a0e628bfcce4ea348876a310cb81335c (diff)
downloadcoreboot-3f5f74d1349625fa33bcbdfd2956d1e36b3f236d.tar.xz
mb/intel/tglrvp: pin mux for ISH
TGL FSP does pin mux for ISH related to pins by UPD(PchIshSpiEnable, PchIshUartEnable, PchIshI2cEnable, PchIshGpEnable) but as default UPD value is disabled, FSP doesn't do pin mux. So pin mux for ISH in gpio.c. Pin mux for ISH for TGLRVP ISHUART0: GPP_D13, GPP_D14 as NF1 ISHI2C0: GPP_B5, GPP_B6 as NF1 ISHGPIO0-7: GPP_D0~D3, GPP_D17~D18, GPP_E15~E16 as NF1 BUG=none BRANCH=none TEST=Build and boot to OS and check pinctl driver to check pin mux. Check ISHUART0, ISHI2C0, ISHGPIO0-7 native function setting. They should be NF1. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I1a9ba3a713527f5ce962659960418cd0f37dd262 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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