diff options
author | Julius Werner <jwerner@chromium.org> | 2018-10-10 15:31:36 -0700 |
---|---|---|
committer | Julius Werner <jwerner@chromium.org> | 2018-10-12 20:14:54 +0000 |
commit | ca52a258822c1c47d533684c5a4cbe5f2b7bd487 (patch) | |
tree | 4017c7a2e999f6a7e58f942a7a789352a6666660 /payloads/libpayload/arch/arm64/mmu.c | |
parent | e1b1ec7154e4c41adf4eb6a0e4ebd08a2e938a2c (diff) | |
download | coreboot-ca52a258822c1c47d533684c5a4cbe5f2b7bd487.tar.xz |
libpayload: arm64: Conform to new coreboot lib_helpers.h and assume EL2
This patch adds the new, faster architectural register accessors to
libpayload that were already added to coreboot in CB:27881. It also
hardcodes the assumption that coreboot payloads run at EL2, which has
already been hardcoded in coreboot with CB:27880 (see rationale there).
This means we can drop all the read_current/write_current stuff which
added a lot of unnecessary helpers to check the current exception level.
This patch breaks payloads that used read_current/write_current
accessors, but it seems unlikely that many payloads deal with this stuff
anyway, and it should be a trivial fix (just replace them with the
respective _el2 versions).
Also add accessors for a couple of more registers that are required to
enable debug mode while I'm here.
Change-Id: Ic9dfa48411f3805747613f03611f8a134a51cc46
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'payloads/libpayload/arch/arm64/mmu.c')
-rw-r--r-- | payloads/libpayload/arch/arm64/mmu.c | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index c860ee0fc8..556f52b610 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -252,7 +252,7 @@ void mmu_config_range(void *start, size_t size, uint64_t tag) /* ARMv8 MMUs snoop L1 data cache, no need to flush it. */ dsb(); - tlbiall_current(); + tlbiall_el2(); dsb(); isb(); } @@ -298,7 +298,7 @@ static uint32_t is_mmu_enabled(void) { uint32_t sctlr; - sctlr = raw_read_sctlr_current(); + sctlr = raw_read_sctlr_el2(); return (sctlr & SCTLR_M); } @@ -309,19 +309,18 @@ static uint32_t is_mmu_enabled(void) */ void mmu_disable(void) { - uint32_t el = get_current_el(); uint32_t sctlr; - sctlr = raw_read_sctlr(el); + sctlr = raw_read_sctlr_el2(); sctlr &= ~(SCTLR_C | SCTLR_M | SCTLR_I); - tlbiall_current(); + tlbiall_el2(); dcache_clean_invalidate_all(); dsb(); isb(); - raw_write_sctlr(sctlr, el); + raw_write_sctlr_el2(sctlr); dcache_clean_invalidate_all(); dsb(); @@ -338,26 +337,26 @@ void mmu_enable(void) uint32_t sctlr; /* Initialize MAIR indices */ - raw_write_mair_current(MAIR_ATTRIBUTES); + raw_write_mair_el2(MAIR_ATTRIBUTES); /* Invalidate TLBs */ - tlbiall_current(); + tlbiall_el2(); /* Initialize TCR flags */ - raw_write_tcr_current(TCR_TOSZ | TCR_IRGN0_NM_WBWAC | TCR_ORGN0_NM_WBWAC | + raw_write_tcr_el2(TCR_TOSZ | TCR_IRGN0_NM_WBWAC | TCR_ORGN0_NM_WBWAC | TCR_SH0_IS | TCR_TG0_4KB | TCR_PS_256TB | TCR_TBI_USED); /* Initialize TTBR */ - raw_write_ttbr0_current((uintptr_t)xlat_addr); + raw_write_ttbr0_el2((uintptr_t)xlat_addr); /* Ensure system register writes are committed before enabling MMU */ isb(); /* Enable MMU */ - sctlr = raw_read_sctlr_current(); + sctlr = raw_read_sctlr_el2(); sctlr |= SCTLR_C | SCTLR_M | SCTLR_I; - raw_write_sctlr_current(sctlr); + raw_write_sctlr_el2(sctlr); isb(); |