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| author | Vadim Bendebury <vbendeb@chromium.org> | 2014-05-27 16:16:50 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-01-06 16:56:23 +0100 |
| commit | b7f82e9559ae7a002330183affc285d6dd0abd1a (patch) | |
| tree | bf8068c7706218d38f5bf547bf510320515a1fdf /payloads/libpayload/arch/arm | |
| parent | 9b29aad5263f2aeba21cf4d521e7798f9dedb2b9 (diff) | |
| download | coreboot-b7f82e9559ae7a002330183affc285d6dd0abd1a.tar.xz | |
libpayload: arm: add code to clear bss
This adds some assembly code to clear .bss segment. It might have been
already cleared by the loader, but it is not guaranteed. This also
helps when the program is loaded by the debugger.
BUG=none
TEST=observed that .bss is now initialized when the program is
restarted. Verified correct boundaries of the segment.
Original-Change-Id: I0aed0070da53881e4cf8c27049459040c006e765
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201784
Original-Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit c89ecee5ddfc33a438d4d1926d3756a48f3c2576)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic0c33d2a8ad22cd23b3ccb73c603cb14ae2aab29
Reviewed-on: http://review.coreboot.org/8060
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'payloads/libpayload/arch/arm')
| -rw-r--r-- | payloads/libpayload/arch/arm/head.S | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/payloads/libpayload/arch/arm/head.S b/payloads/libpayload/arch/arm/head.S index c5c96ea38f..788e328322 100644 --- a/payloads/libpayload/arch/arm/head.S +++ b/payloads/libpayload/arch/arm/head.S @@ -34,14 +34,25 @@ */ ENTRY(_entry) + /* TODO: disable interrupts */ + + /* Clear BSS */ + mov r12, #0 + ldr r2, bss_boundaries + ldr r3, bss_boundaries + 4 + cmp r2, r3 + beq no_bss + + sub r3, #4 /* Account for late condition check. */ +loop: + cmp r2, r3 + str r12, [r2], #4 + blt loop +no_bss: /* Save off the location of the coreboot tables */ ldr r1, 1f str r0, [r1] - /* TODO: disable interrupts */ - - /* TODO: Clear BSS */ - /* Setup new stack */ ldr sp, 2f @@ -59,6 +70,9 @@ ENTRY(_entry) ENDPROC(_entry) .align 4 +bss_boundaries: + .word _edata + .word _end 1: .word cb_header_ptr 2: |