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authorJulius Werner <jwerner@chromium.org>2014-10-22 14:12:50 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-04-10 07:50:21 +0200
commit120aec0902663d2ed942c1542217791c46b8e406 (patch)
tree8ed8ab12743869df69d509f43a35799526b570cf /payloads/libpayload/configs/defconfig-mips
parent907fd12cf6c10b2a3d1edec09b23be5eeb4b9643 (diff)
downloadcoreboot-120aec0902663d2ed942c1542217791c46b8e406.tar.xz
serial: Combine Tegra and Rockchip UARTs to generic 8250_mmio32
We have two drivers for a 100%-identical peripheral right now, mostly because we couldn't come up with a good common name for it back when we checked it in. That seems like a pretty silly reason in the long run. Both Tegra and Rockchip SoCs contain UARTs that use the common 8250 register interface (at least for the very basic byte-per-byte transmit and receive parts we care about), memory-mapped with a 32-bit register stride. This patch combines them to a single 8250_mmio32 driver (which also fixes a problem when booting Rockchip without serial enabled, since that driver forgot to check for serial initialization when registering its console drivers). The register accesses are done using readl/writel (as Rockchip did before), since the registers are documented as 32-bit length (with top 24 bits RAZ/WI), although the Tegra SoC doesn't enforce APB accesses to have the full word length. Also fixed checkpatch stuff. A day may come when we can also merge this driver into the (completely different, with more complicated features and #ifdefs) 8250 driver for x86 (which has MMIO support for 8-bit register stride only), both here and in coreboot. But it is not this day. This day I just want to get rid of a 99% identical file without expending too much effort. BUG=None TEST=Booted on Veyron_Pinky and Nyan_Blaze with and without serial enabled, both worked fine (although Veyron has another kernel issue). Change-Id: I85c004a75cc5aa7cb40098002d3e00a62c1c5f2d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e7959c19356d2922aa414866016540ad9ee2ffa8 Original-Change-Id: Ib84d00f52ff2c48398c75f77f6a245e658ffdeb9 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225102 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9387 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'payloads/libpayload/configs/defconfig-mips')
-rw-r--r--payloads/libpayload/configs/defconfig-mips3
1 files changed, 1 insertions, 2 deletions
diff --git a/payloads/libpayload/configs/defconfig-mips b/payloads/libpayload/configs/defconfig-mips
index 0af1a91706..76b8474010 100644
--- a/payloads/libpayload/configs/defconfig-mips
+++ b/payloads/libpayload/configs/defconfig-mips
@@ -40,8 +40,7 @@ CONFIG_LP_CBMEM_CONSOLE=y
CONFIG_LP_SERIAL_CONSOLE=y
CONFIG_LP_8250_SERIAL_CONSOLE=y
# CONFIG_LP_S5P_SERIAL_CONSOLE is not set
-# CONFIG_LP_TEGRA_SERIAL_CONSOLE is not set
-# CONFIG_LP_RK_SERIAL_CONSOLE is not set
+# CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE is not set
# CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set
# CONFIG_LP_PL011_SERIAL_CONSOLE is not set
# CONFIG_LP_SERIAL_SET_SPEED is not set