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authorJulius Werner <jwerner@chromium.org>2014-10-22 14:12:50 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-04-10 07:50:21 +0200
commit120aec0902663d2ed942c1542217791c46b8e406 (patch)
tree8ed8ab12743869df69d509f43a35799526b570cf /payloads/libpayload/drivers/serial
parent907fd12cf6c10b2a3d1edec09b23be5eeb4b9643 (diff)
downloadcoreboot-120aec0902663d2ed942c1542217791c46b8e406.tar.xz
serial: Combine Tegra and Rockchip UARTs to generic 8250_mmio32
We have two drivers for a 100%-identical peripheral right now, mostly because we couldn't come up with a good common name for it back when we checked it in. That seems like a pretty silly reason in the long run. Both Tegra and Rockchip SoCs contain UARTs that use the common 8250 register interface (at least for the very basic byte-per-byte transmit and receive parts we care about), memory-mapped with a 32-bit register stride. This patch combines them to a single 8250_mmio32 driver (which also fixes a problem when booting Rockchip without serial enabled, since that driver forgot to check for serial initialization when registering its console drivers). The register accesses are done using readl/writel (as Rockchip did before), since the registers are documented as 32-bit length (with top 24 bits RAZ/WI), although the Tegra SoC doesn't enforce APB accesses to have the full word length. Also fixed checkpatch stuff. A day may come when we can also merge this driver into the (completely different, with more complicated features and #ifdefs) 8250 driver for x86 (which has MMIO support for 8-bit register stride only), both here and in coreboot. But it is not this day. This day I just want to get rid of a 99% identical file without expending too much effort. BUG=None TEST=Booted on Veyron_Pinky and Nyan_Blaze with and without serial enabled, both worked fine (although Veyron has another kernel issue). Change-Id: I85c004a75cc5aa7cb40098002d3e00a62c1c5f2d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e7959c19356d2922aa414866016540ad9ee2ffa8 Original-Change-Id: Ib84d00f52ff2c48398c75f77f6a245e658ffdeb9 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225102 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9387 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'payloads/libpayload/drivers/serial')
-rw-r--r--payloads/libpayload/drivers/serial/8250_mmio32.c (renamed from payloads/libpayload/drivers/serial/tegra.c)48
-rw-r--r--payloads/libpayload/drivers/serial/rk_serial.c115
2 files changed, 24 insertions, 139 deletions
diff --git a/payloads/libpayload/drivers/serial/tegra.c b/payloads/libpayload/drivers/serial/8250_mmio32.c
index a3dad2b09f..285f7f6dac 100644
--- a/payloads/libpayload/drivers/serial/tegra.c
+++ b/payloads/libpayload/drivers/serial/8250_mmio32.c
@@ -28,7 +28,7 @@
#include <libpayload.h>
#include <stdint.h>
-struct tegra_uart {
+struct mmio32_uart {
union {
uint32_t thr; // Transmit holding register.
uint32_t rbr; // Receive buffer register.
@@ -49,47 +49,47 @@ struct tegra_uart {
} __attribute__ ((packed));
enum {
- TEGRA_UART_LSR_DR = 0x1 << 0, // Data ready.
- TEGRA_UART_LSR_OE = 0x1 << 1, // Overrun.
- TEGRA_UART_LSR_PE = 0x1 << 2, // Parity error.
- TEGRA_UART_LSR_FE = 0x1 << 3, // Framing error.
- TEGRA_UART_LSR_BI = 0x1 << 4, // Break.
- TEGRA_UART_LSR_THRE = 0x1 << 5, // Xmit holding register empty.
- TEGRA_UART_LSR_TEMT = 0x1 << 6, // Xmitter empty.
- TEGRA_UART_LSR_ERR = 0x1 << 7 // Error.
+ LSR_DR = 0x1 << 0, // Data ready.
+ LSR_OE = 0x1 << 1, // Overrun.
+ LSR_PE = 0x1 << 2, // Parity error.
+ LSR_FE = 0x1 << 3, // Framing error.
+ LSR_BI = 0x1 << 4, // Break.
+ LSR_THRE = 0x1 << 5, // Xmit holding register empty.
+ LSR_TEMT = 0x1 << 6, // Xmitter empty.
+ LSR_ERR = 0x1 << 7 // Error.
};
-static struct tegra_uart *uart_regs;
+static struct mmio32_uart *uart = NULL;
void serial_putchar(unsigned int c)
{
- while (!(readb(&uart_regs->lsr) & TEGRA_UART_LSR_THRE));
- writeb(c, &uart_regs->thr);
+ while (!(readl(&uart->lsr) & LSR_THRE))
+ /* wait for transmit register to clear */;
+
+ writel((char)c, &uart->thr);
if (c == '\n')
serial_putchar('\r');
}
int serial_havechar(void)
{
- uint8_t lsr = readb(&uart_regs->lsr);
- return (lsr & TEGRA_UART_LSR_DR) == TEGRA_UART_LSR_DR;
+ uint8_t lsr = readl(&uart->lsr);
+ return (lsr & LSR_DR) == LSR_DR;
}
int serial_getchar(void)
{
while (!serial_havechar())
- {;}
+ /* wait for character */;
- return readb(&uart_regs->rbr);
+ return readl(&uart->rbr);
}
-static struct console_output_driver tegra_serial_output =
-{
+static struct console_output_driver mmio32_serial_output = {
.putchar = &serial_putchar
};
-static struct console_input_driver tegra_serial_input =
-{
+static struct console_input_driver mmio32_serial_input = {
.havekey = &serial_havechar,
.getchar = &serial_getchar
};
@@ -99,15 +99,15 @@ void serial_init(void)
if (!lib_sysinfo.serial || !lib_sysinfo.serial->baseaddr)
return;
- uart_regs = (struct tegra_uart *)(uintptr_t)lib_sysinfo.serial->baseaddr;
+ uart = (struct mmio32_uart *)(uintptr_t)lib_sysinfo.serial->baseaddr;
}
void serial_console_init(void)
{
serial_init();
- if (uart_regs) {
- console_add_output_driver(&tegra_serial_output);
- console_add_input_driver(&tegra_serial_input);
+ if (uart) {
+ console_add_output_driver(&mmio32_serial_output);
+ console_add_input_driver(&mmio32_serial_input);
}
}
diff --git a/payloads/libpayload/drivers/serial/rk_serial.c b/payloads/libpayload/drivers/serial/rk_serial.c
deleted file mode 100644
index 91a6e1bde9..0000000000
--- a/payloads/libpayload/drivers/serial/rk_serial.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Rockchip Electronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-#include <libpayload-config.h>
-#include <libpayload.h>
-struct rk_uart {
- union {
- u32 uart_thr; /* Transmit holding register. */
- u32 uart_rbr; /* Receive buffer register. */
- u32 uart_dll; /* Divisor latch lsb. */
- };
- union {
- u32 uart_ier; /* Interrupt enable register. */
- u32 uart_dlh; /* Divisor latch msb. */
- };
- union {
- uint32_t uart_iir; /* Interrupt identification register. */
- uint32_t uart_fcr; /* FIFO control register. */
- };
- u32 uart_lcr;
- u32 uart_mcr;
- u32 uart_lsr;
- u32 uart_msr;
- u32 uart_scr;
- u32 reserved1[(0x30 - 0x20) / 4];
- u32 uart_srbr[(0x70 - 0x30) / 4];
- u32 uart_far;
- u32 uart_tfr;
- u32 uart_rfw;
- u32 uart_usr;
- u32 uart_tfl;
- u32 uart_rfl;
- u32 uart_srr;
- u32 uart_srts;
- u32 uart_sbcr;
- u32 uart_sdmam;
- u32 uart_sfe;
- u32 uart_srt;
- u32 uart_stet;
- u32 uart_htx;
- u32 uart_dmasa;
- u32 reserver2[(0xf4 - 0xac) / 4];
- u32 uart_cpr;
- u32 uart_ucv;
- u32 uart_ctr;
-};
-enum {
- UART_LSR_DR = 0x1 << 0, /* Data ready. */
- UART_LSR_OE = 0x1 << 1, /* Overrun. */
- UART_LSR_PE = 0x1 << 2, /* Parity error. */
- UART_LSR_FE = 0x1 << 3, /* Framing error. */
- UART_LSR_BI = 0x1 << 4, /* Break. */
- UART_LSR_THRE = 0x1 << 5, /* Xmit holding register empty. */
- UART_LSR_TEMT = 0x1 << 6, /* Xmitter empty. */
- UART_LSR_ERR = 0x1 << 7 /* Error. */
-};
-
-static struct rk_uart *uart_regs;
-void serial_putchar(unsigned int c)
-{
- while (!(readl(&uart_regs->uart_lsr) & UART_LSR_THRE));
- writel((c & 0xff), &uart_regs->uart_thr);
- if (c == '\n')
- serial_putchar('\r');
-}
-
-int serial_havechar(void)
-{
- uint8_t lsr = readl(&uart_regs->uart_lsr);
- return (lsr & UART_LSR_DR) == UART_LSR_DR;
-}
-
-int serial_getchar(void)
-{
- while (!serial_havechar());
- return readl(&uart_regs->uart_rbr)&0xff;
-}
-
-static struct console_input_driver consin = {
- .havekey = &serial_havechar,
- .getchar = &serial_getchar
-};
-
-static struct console_output_driver consout = {.putchar = &serial_putchar
-};
-
-void serial_init(void)
-{
- if (!lib_sysinfo.serial || !lib_sysinfo.serial->baseaddr)
- return;
-
- uart_regs = (struct rk_uart *)lib_sysinfo.serial->baseaddr;
-}
-
-void serial_console_init(void)
-{
- serial_init();
- console_add_input_driver(&consin);
- console_add_output_driver(&consout);
-}