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authorVadim Bendebury <vbendeb@chromium.org>2014-05-23 14:18:35 -0700
committerMarc Jones <marc.jones@se-eng.com>2015-01-04 00:27:50 +0100
commit11aaf1f42ad8035c2870dc50852437f5e8863061 (patch)
tree5b39011faeed8d3601e5449f9a9c62093cd06a81 /payloads/libpayload/drivers/timer
parent66fdbced5e61ad2387bfae2db7caf507fef88f37 (diff)
downloadcoreboot-11aaf1f42ad8035c2870dc50852437f5e8863061.tar.xz
ipq8064: Add work around for slow timer clock
Libpayload libc requires timer clock frequency to be at least 1MHz. Ipq8064 code presently provides a single option of 32kHz. Pretend to be running at 1 MHz without additional accuracy. This is a hack which will be reverted as soon as the SOC is configured to supply a faster running clock. BUG=chrome-os-partner:27784, chrome-os-partner:28880 TEST=with other changes depthcharge boots to the CLI console Original-Change-Id: I80ec6652bc5693a549668cd6e824e9cf5c26b182 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201342 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 466a59967b13986099106f8b44924648c1e6e6cd) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I113689191db70710e7a45ccd02d672f482343e35 Reviewed-on: http://review.coreboot.org/8004 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'payloads/libpayload/drivers/timer')
-rw-r--r--payloads/libpayload/drivers/timer/ipq806x.c22
1 files changed, 20 insertions, 2 deletions
diff --git a/payloads/libpayload/drivers/timer/ipq806x.c b/payloads/libpayload/drivers/timer/ipq806x.c
index 4edbf8eda0..0d70a86813 100644
--- a/payloads/libpayload/drivers/timer/ipq806x.c
+++ b/payloads/libpayload/drivers/timer/ipq806x.c
@@ -29,13 +29,31 @@
#include <libpayload.h>
+/*
+ * TODO(vbendeb): reverted this hack once proper timer code is in place (see
+ * http://crosbug.com/p/28880 for details.
+ */
+#define MIN_TIMER_FREQ 1000000
+
uint64_t timer_hz(void)
{
- return CONFIG_LP_IPQ806X_TIMER_FREQ;
+ return (CONFIG_LP_IPQ806X_TIMER_FREQ >= MIN_TIMER_FREQ) ?
+ CONFIG_LP_IPQ806X_TIMER_FREQ : MIN_TIMER_FREQ;
}
uint64_t timer_raw_value(void)
{
- return readl((void *)CONFIG_LP_IPQ806X_TIMER_REG);
+ uint64_t rawv = readl((void *)CONFIG_LP_IPQ806X_TIMER_REG);
+
+ /*
+ * This is extremely crude, but it kicks in only for the case when the
+ * timer clock frequency is below 1MHz, which should never be the case
+ * on a properly configured system. The compiler will eliminate the
+ * check as long as config value exceeds 1MHz.
+ */
+ if (CONFIG_LP_IPQ806X_TIMER_FREQ < MIN_TIMER_FREQ)
+ rawv *= (MIN_TIMER_FREQ / CONFIG_LP_IPQ806X_TIMER_FREQ);
+
+ return rawv;
}