diff options
author | huang lin <hl@rock-chips.com> | 2014-12-04 18:25:47 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-14 10:42:58 +0200 |
commit | 8b52c93a73f494364e43833f924fbd13e20530bc (patch) | |
tree | e57c40fa54b91619c246b11dcc678e5dddad9186 /payloads/libpayload/drivers/usb/dwc2.c | |
parent | 365250e61ec8b87a4355fca8cea32c9ae57eca05 (diff) | |
download | coreboot-8b52c93a73f494364e43833f924fbd13e20530bc.tar.xz |
libpayload dwc2: Use a new FIFO allocation method
Total FIFO length is split into 512 byte blocks.
Allocate these blocks to GRXFSIZ and GNPTXFSZ evenly.
This method avoids hardcoding and makes the FIFO size value
work for dwc2 controllers that have a different FIFO ram size.
BUG=chrome-os-partner:32634
BRANCH=None
TEST=Boot kernel from USB
Change-Id: I78ce0fa4c4600fb56c991874a93bdd6674e648c2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5645a25e95f84359cd10fc9fcf56e1f73fd6ce87
Original-Change-Id: Ib50a08c193f7f65392810ca3528a97554f2c3999
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/233119
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9454
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'payloads/libpayload/drivers/usb/dwc2.c')
-rw-r--r-- | payloads/libpayload/drivers/usb/dwc2.c | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c index 1092cb4ee3..71c4967e7e 100644 --- a/payloads/libpayload/drivers/usb/dwc2.c +++ b/payloads/libpayload/drivers/usb/dwc2.c @@ -35,11 +35,12 @@ static void dwc2_reinit(hci_t *controller) gintsts_t gintsts = { .d32 = 0 }; gahbcfg_t gahbcfg = { .d32 = 0 }; grxfsiz_t grxfsiz = { .d32 = 0 }; + ghwcfg3_t hwcfg3 = { .d32 = 0 }; hcintmsk_t hcintmsk = { .d32 = 0 }; gnptxfsiz_t gnptxfsiz = { .d32 = 0 }; const int timeout = 10000; - int i; + int i, fifo_blocks, tx_blocks; /* Wait for AHB idle */ for (i = 0; i < timeout; i++) { @@ -86,10 +87,24 @@ static void dwc2_reinit(hci_t *controller) * The non-periodic tx fifo and rx fifo share one continuous * piece of IP-internal SRAM. */ - grxfsiz.rxfdep = DWC2_RXFIFO_DEPTH; + + /* + * Read total data FIFO depth from HWCFG3 + * this value is in terms of 32-bit words + */ + hwcfg3.d32 = readl(®->core.ghwcfg3); + /* + * Reserve 2 spaces for the status entries of received packets + * and 2 spaces for bulk and control OUT endpoints. Calculate how + * many blocks can be alloted, assume largest packet size is 512. + */ + fifo_blocks = (hwcfg3.dfifodepth - 4) / (512 / 4); + tx_blocks = fifo_blocks / 2; + + grxfsiz.rxfdep = (fifo_blocks - tx_blocks) * (512 / 4) + 4; writel(grxfsiz.d32, ®->core.grxfsiz); - gnptxfsiz.nptxfstaddr = DWC2_RXFIFO_DEPTH; - gnptxfsiz.nptxfdep = DWC2_NPTXFIFO_DEPTH; + gnptxfsiz.nptxfstaddr = grxfsiz.rxfdep; + gnptxfsiz.nptxfdep = tx_blocks * (512 / 4); writel(gnptxfsiz.d32, ®->core.gnptxfsiz); /* Init host channels */ |