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author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-01-19 02:41:49 +0000 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-21 11:09:07 +0100 |
commit | bde2081e753b90734af9f198b1ae84d26930363d (patch) | |
tree | 6c2edaa02b0dbd8f191f33d5b98e5ecee8614c43 /payloads/libpayload/include/mips | |
parent | b29a67d8c87d1e66042bab3029bbb5b82bd4e972 (diff) | |
download | coreboot-bde2081e753b90734af9f198b1ae84d26930363d.tar.xz |
libpayload: mips: correct platform ID
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; behaves as expected.
BRANCH=none
Change-Id: I8e5ac80e95b5169102eaa075bc22045c0789d486
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4afe332bcc41afeb7e31e918e345c3336f7dc604
Original-Change-Id: I55b788faf7984bafc2509cac69867a772c7cb863
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/241427
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8745
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'payloads/libpayload/include/mips')
-rw-r--r-- | payloads/libpayload/include/mips/arch/cpu.h | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/payloads/libpayload/include/mips/arch/cpu.h b/payloads/libpayload/include/mips/arch/cpu.h index 952ec7c528..93e42ea455 100644 --- a/payloads/libpayload/include/mips/arch/cpu.h +++ b/payloads/libpayload/include/mips/arch/cpu.h @@ -22,8 +22,15 @@ * Reading at this address allows to identify the platform the code is running * on */ -#define IMG_PLATFORM_ID() (*((unsigned *)0xB8149060)) -#define IMG_PLATFORM_ID_SILICON 0xF00D0006 + +/* + * This register holds the FPGA image version + * If we're not working on the FPGA this will be 0 + */ +#define PRIMARY_FPGA_VERSION 0xB8149060 +#define IMG_PLATFORM_ID() read32(PRIMARY_FPGA_VERSION) +#define IMG_PLATFORM_ID_FPGA 0xD1400003 /* Last FPGA image */ +#define IMG_PLATFORM_ID_SILICON 0 #define CP0_COUNT 9 #define CP0_COMPARE 11 |