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authorPatrick Rudolph <patrick.rudolph@9elements.com>2018-03-05 09:53:47 +0100
committerDavid Hendricks <david.hendricks@gmail.com>2018-03-23 04:09:50 +0000
commit57afc5e0f2309ba9f7fbd171642f04c6da9d9976 (patch)
treeaeeafda4fee623141e5a8c162f7612b6454918e7 /payloads/libpayload/include
parent3d9462a07f0250cf628b7874620f9f682b7a020e (diff)
downloadcoreboot-57afc5e0f2309ba9f7fbd171642f04c6da9d9976.tar.xz
arch/arm64/armv8/mmu: Add support for 48bit VA
The VA space needs to be extended to support 48bit, as on Cavium SoCs the MMIO starts at 1 << 47. The following changes were done to coreboot and libpayload: * Use page table lvl 0 * Increase VA bits to 48 * Enable 256TB in MMU controller * Add additional asserts Tested on Cavium SoC and two ARM64 Chromebooks. Change-Id: I89e6a4809b6b725c3945bad7fce82b0dfee7c262 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/24970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'payloads/libpayload/include')
-rw-r--r--payloads/libpayload/include/arm64/arch/mmu.h9
1 files changed, 4 insertions, 5 deletions
diff --git a/payloads/libpayload/include/arm64/arch/mmu.h b/payloads/libpayload/include/arm64/arch/mmu.h
index 2f87d09681..3cea696f64 100644
--- a/payloads/libpayload/include/arm64/arch/mmu.h
+++ b/payloads/libpayload/include/arm64/arch/mmu.h
@@ -83,7 +83,7 @@ extern char _start[], _end[];
/* XLAT Table Init Attributes */
#define VA_START 0x0
-#define BITS_PER_VA 33
+#define BITS_PER_VA 48
#define MIN_64_BIT_ADDR (1UL << 32)
/* Granule size of 4KB is being used */
#define GRANULE_SIZE_SHIFT 12
@@ -92,14 +92,12 @@ extern char _start[], _end[];
#define GRANULE_SIZE_MASK ((1 << GRANULE_SIZE_SHIFT) - 1)
#define BITS_RESOLVED_PER_LVL (GRANULE_SIZE_SHIFT - 3)
+#define L0_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 3)
#define L1_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 2)
#define L2_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 1)
#define L3_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 0)
-#if BITS_PER_VA > L1_ADDR_SHIFT + BITS_RESOLVED_PER_LVL
- #error "BITS_PER_VA too large (we don't have L0 table support)"
-#endif
-
+#define L0_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L0_ADDR_SHIFT)
#define L1_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L1_ADDR_SHIFT)
#define L2_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L2_ADDR_SHIFT)
#define L3_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L3_ADDR_SHIFT)
@@ -109,6 +107,7 @@ extern char _start[], _end[];
#define L3_XLAT_SIZE (1UL << L3_ADDR_SHIFT)
#define L2_XLAT_SIZE (1UL << L2_ADDR_SHIFT)
#define L1_XLAT_SIZE (1UL << L1_ADDR_SHIFT)
+#define L0_XLAT_SIZE (1UL << L0_ADDR_SHIFT)
/* Block indices required for MAIR */
#define BLOCK_INDEX_MEM_DEV_NGNRNE 0