libpayload arm64: Add library helpers

Add library helpers to access standard arm64 registers. This library also
provides functions to directly read/write register based on current el. So, rest
of the code doesnt need to keep checking the el and call appropriate function
based on that.

BUG=chrome-os-partner:31634
BRANCH=None
TEST=Libpayload and depthcharge compile successfully for ryu

Change-Id: Ibc0ca49f158362d4b7ab2045bf0fbd58ada79360
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2ca6da580cb51b4c23abdaf04fee2785e5780510
Original-Change-Id: I9b63e04aa26a98bbeb34fdef634776d49454ca8d
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214575
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8784
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

3 files changed, 320 insertions, 126 deletions

diff --git a/payloads/libpayload/include/arm64/arch/cache.h b/payloads/libpayload/include/arm64/arch/cache.h
index f03d09b9f9..5a0b3b03ba 100644
--- a/payloads/libpayload/include/arm64/arch/cache.h
+++ b/payloads/libpayload/include/arm64/arch/cache.h
@@ -68,132 +68,6 @@
 /* Bit 31 is reserved */
 
 /*
- * Sync primitives
- */
-/* data memory barrier */
-#define dmb_opt(opt)  asm volatile ("dmb " #opt : : : "memory")
-/* data sync barrier */
-#define dsb_opt(opt)  asm volatile ("dsb " #opt : : : "memory")
-/* instruction sync barrier */
-#define isb_opt(opt)  asm volatile ("isb " #opt : : : "memory")
-
-#define dmb() dmb_opt(sy)
-#define dsb() dsb_opt(sy)
-#define isb() isb_opt()
-
-/*
- * Low-level TLB maintenance operations
- */
-
-/* invalidate entire unified TLB */
-static inline void tlbiall_el3(void)
-{
-	asm volatile ("tlbi alle3" : : : "memory");
-}
-
-/* invalidate unified TLB by VA, all ASID */
-static inline void tlbivaa(unsigned long va)
-{
-	asm volatile ("tlbi vaae1, %0" : : "r" (va) : "memory");
-}
-
-/*
- * Low-level cache maintenance operations
- */
-
-/* data cache clean and invalidate by VA to PoC */
-static inline void dccivac(unsigned long va)
-{
-	asm volatile ("dc civac, %0" : : "r" (va) : "memory");
-}
-
-/* data cache invalidate by set/way */
-static inline void dccisw(uint32_t val)
-{
-	asm volatile ("dc cisw, %0" : : "r" (val) : "memory");
-}
-
-/* data cache clean by VA to PoC */
-static inline void dccvac(unsigned long va)
-{
-	asm volatile ("dc cvac, %0" : : "r" (va) : "memory");
-}
-
-/* data cache clean by set/way */
-static inline void dccsw(uint32_t val)
-{
-	asm volatile ("dc csw, %0" : : "r" (val) : "memory");
-}
-
-/* data cache invalidate by VA to PoC */
-static inline void dcivac(unsigned long va)
-{
-	asm volatile ("dc ivac, %0" : : "r" (va) : "memory");
-}
-
-/* data cache invalidate by set/way */
-static inline void dcisw(uint32_t val)
-{
-	asm volatile ("dc isw, %0" : : "r" (val) : "memory");
-}
-
-/* instruction cache invalidate all by PoU */
-static inline void iciallu(void)
-{
-	asm volatile ("ic iallu" : : "r" (0));
-}
-
-/* read cache level ID register (CLIDR) */
-static inline uint32_t read_clidr(void)
-{
-	uint32_t val = 0;
-	asm volatile ("mrs %0, clidr_el1" : "=r" (val));
-	return val;
-}
-
-/* read cache size ID register register (CCSIDR) */
-static inline uint32_t read_ccsidr(void)
-{
-	uint32_t val = 0;
-	asm volatile ("mrs %0, ccsidr_el1" : "=r" (val));
-	return val;
-}
-
-/* read cache size selection register (CSSELR) */
-static inline uint32_t read_csselr(void)
-{
-	uint32_t val = 0;
-	asm volatile ("mrs %0, csselr_el1" : "=r" (val));
-	return val;
-}
-
-/* write to cache size selection register (CSSELR) */
-static inline void write_csselr(uint32_t val)
-{
-	/*
-	 * Bits [3:1] - Cache level + 1 (0b000 = L1, 0b110 = L7, 0b111 is rsvd)
-	 * Bit 0 - 0 = data or unified cache, 1 = instruction cache
-	 */
-	asm volatile ("msr csselr_el1, %0" : : "r" (val));
-	isb();	/* ISB to sync the change to CCSIDR */
-}
-
-/* read system control register (SCTLR) */
-static inline uint32_t read_sctlr_el3(void)
-{
-	uint32_t val;
-	asm volatile ("mrs %0, sctlr_el3" : "=r" (val));
-	return val;
-}
-
-/* write system control register (SCTLR) */
-static inline void write_sctlr_el3(uint32_t val)
-{
-	asm volatile ("msr sctlr_el3, %0" : : "r" (val) : "cc");
-	isb();
-}
-
-/*
  * Cache maintenance API
  */
 
diff --git a/payloads/libpayload/include/arm64/arch/io.h b/payloads/libpayload/include/arm64/arch/io.h
index df3a0d51ae..f8be1aec95 100644
--- a/payloads/libpayload/include/arm64/arch/io.h
+++ b/payloads/libpayload/include/arm64/arch/io.h
@@ -33,6 +33,7 @@
 
 #include <stdint.h>
 #include <arch/cache.h>
+#include <arch/lib_helpers.h>
 
 static inline uint8_t readb(volatile const void *_a)
 {
diff --git a/payloads/libpayload/include/arm64/arch/lib_helpers.h b/payloads/libpayload/include/arm64/arch/lib_helpers.h
new file mode 100644
index 0000000000..f8d95468e1
--- /dev/null
+++ b/payloads/libpayload/include/arm64/arch/lib_helpers.h
@@ -0,0 +1,319 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * lib_helpers.h: All library function prototypes and macros are defined in this
+ * file.
+ */
+
+#ifndef __ARCH_LIB_HELPERS_H__
+#define __ARCH_LIB_HELPERS_H__
+
+#define EL0               0
+#define EL1               1
+#define EL2               2
+#define EL3               3
+
+#define CURRENT_EL_MASK   0x3
+#define CURRENT_EL_SHIFT  2
+
+#define DAIF_DBG_BIT      (1<<3)
+#define DAIF_ABT_BIT      (1<<2)
+#define DAIF_IRQ_BIT      (1<<1)
+#define DAIF_FIQ_BIT      (1<<0)
+
+#define SWITCH_CASE_READ(func,var,type)	 do {	\
+	type var = -1;				\
+	uint8_t current_el = get_current_el();	\
+	switch(current_el) {			\
+        case EL1:				\
+		var = func##_el1();		\
+			break;			\
+        case EL2:				\
+		var = func##_el2();		\
+			break;			\
+        case EL3:                               \
+		var = func##_el3();		\
+			break;			\
+	}					\
+	return var;				\
+	} while(0)
+
+#define SWITCH_CASE_WRITE(func,var)	do {   \
+	uint8_t current_el = get_current_el(); \
+	switch(current_el) {		       \
+	case EL1:			       \
+		func##_el1(var);	       \
+			break;		       \
+        case EL2:			       \
+		func##_el2(var);	       \
+			break;		       \
+        case EL3:			       \
+		func##_el3(var);	       \
+			break;		       \
+	}				       \
+	} while(0)
+
+#define SWITCH_CASE_TLBI(func) do {		\
+	uint8_t current_el = get_current_el();	\
+	switch(current_el) {			\
+        case EL1:        			\
+		func##_el1();			\
+			break;			\
+        case EL2:        			\
+		func##_el2();			\
+			break;			\
+        case EL3:        			\
+		func##_el3();			\
+			break;			\
+	}					\
+	} while(0)
+
+/* PSTATE and special purpose register access functions */
+uint32_t raw_read_current_el(void);
+uint32_t get_current_el(void);
+uint32_t raw_read_daif(void);
+void raw_write_daif(uint32_t daif);
+void enable_debug_exceptions(void);
+void enable_serror_exceptions(void);
+void enable_irq(void);
+void enable_fiq(void);
+void disable_debug_exceptions(void);
+void disable_serror_exceptions(void);
+void disable_irq(void);
+void disable_fiq(void);
+uint64_t raw_read_dlr_el0(void);
+void raw_write_dlr_el0(uint64_t dlr_el0);
+uint64_t raw_read_dspsr_el0(void);
+void raw_write_dspsr_el0(uint64_t dspsr_el0);
+uint64_t raw_read_elr_el1(void);
+void raw_write_elr_el1(uint64_t elr_el1);
+uint64_t raw_read_elr_el2(void);
+void raw_write_elr_el2(uint64_t elr_el2);
+uint64_t raw_read_elr_el3(void);
+void raw_write_elr_el3(uint64_t elr_el3);
+uint64_t raw_read_elr_current(void);
+void raw_write_elr_current(uint64_t elr);
+uint32_t raw_read_fpcr(void);
+void raw_write_fpcr(uint32_t fpcr);
+uint32_t raw_read_fpsr(void);
+void raw_write_fpsr(uint32_t fpsr);
+uint32_t raw_read_nzcv(void);
+void raw_write_nzcv(uint32_t nzcv);
+uint64_t raw_read_sp_el0(void);
+void raw_write_sp_el0(uint64_t sp_el0);
+uint64_t raw_read_sp_el1(void);
+void raw_write_sp_el1(uint64_t sp_el1);
+uint64_t raw_read_sp_el2(void);
+void raw_write_sp_el2(uint64_t sp_el2);
+uint32_t raw_read_spsel(void);
+void raw_write_spsel(uint32_t spsel);
+uint64_t raw_read_sp_el3(void);
+void raw_write_sp_el3(uint64_t sp_el3);
+uint32_t raw_read_spsr_abt(void);
+void raw_write_spsr_abt(uint32_t spsr_abt);
+uint32_t raw_read_spsr_el1(void);
+void raw_write_spsr_el1(uint32_t spsr_el1);
+uint32_t raw_read_spsr_el2(void);
+void raw_write_spsr_el2(uint32_t spsr_el2);
+uint32_t raw_read_spsr_el3(void);
+void raw_write_spsr_el3(uint32_t spsr_el3);
+uint32_t raw_read_spsr_current(void);
+void raw_write_spsr_current(uint32_t spsr);
+uint32_t raw_read_spsr_fiq(void);
+void raw_write_spsr_fiq(uint32_t spsr_fiq);
+uint32_t raw_read_spsr_irq(void);
+void raw_write_spsr_irq(uint32_t spsr_irq);
+uint32_t raw_read_spsr_und(void);
+void raw_write_spsr_und(uint32_t spsr_und);
+
+/* System control register access */
+uint32_t raw_read_actlr_el1(void);
+void raw_write_actlr_el1(uint32_t actlr_el1);
+uint32_t raw_read_actlr_el2(void);
+void raw_write_actlr_el2(uint32_t actlr_el2);
+uint32_t raw_read_actlr_el3(void);
+void raw_write_actlr_el3(uint32_t actlr_el3);
+uint32_t raw_read_actlr_current(void);
+void raw_write_actlr_current(uint32_t actlr);
+uint32_t raw_read_afsr0_el1(void);
+void raw_write_afsr0_el1(uint32_t afsr0_el1);
+uint32_t raw_read_afsr0_el2(void);
+void raw_write_afsr0_el2(uint32_t afsr0_el2);
+uint32_t raw_read_afsr0_el3(void);
+void raw_write_afsr0_el3(uint32_t afsr0_el3);
+uint32_t raw_read_afsr0_current(void);
+void raw_write_afsr0_current(uint32_t afsr0);
+uint32_t raw_read_afsr1_el1(void);
+void raw_write_afsr1_el1(uint32_t afsr1_el1);
+uint32_t raw_read_afsr1_el2(void);
+void raw_write_afsr1_el2(uint32_t afsr1_el2);
+uint32_t raw_read_afsr1_el3(void);
+void raw_write_afsr1_el3(uint32_t afsr1_el3);
+uint32_t raw_read_afsr1_current(void);
+void raw_write_afsr1_current(uint32_t afsr1);
+uint32_t raw_read_aidr_el1(void);
+uint64_t raw_read_amair_el1(void);
+void raw_write_amair_el1(uint64_t amair_el1);
+uint64_t raw_read_amair_el2(void);
+void raw_write_amair_el2(uint64_t amair_el2);
+uint64_t raw_read_amair_el3(void);
+void raw_write_amair_el3(uint64_t amair_el3);
+uint64_t raw_read_amair_current(void);
+void raw_write_amair_current(uint64_t amair);
+uint32_t raw_read_ccsidr_el1(void);
+uint32_t raw_read_clidr_el1(void);
+uint32_t raw_read_cpacr_el1(void);
+void raw_write_cpacr_el1(uint32_t cpacr_el1);
+uint32_t raw_read_cptr_el2(void);
+void raw_write_cptr_el2(uint32_t cptr_el2);
+uint32_t raw_read_cptr_el3(void);
+void raw_write_cptr_el3(uint32_t cptr_el3);
+uint32_t raw_read_cptr_current(void);
+void raw_write_cptr_current(uint32_t cptr);
+uint32_t raw_read_csselr_el1(void);
+void raw_write_csselr_el1(uint32_t csselr_el1);
+uint32_t raw_read_ctr_el0(void);
+uint32_t raw_read_esr_el1(void);
+void raw_write_esr_el1(uint32_t esr_el1);
+uint32_t raw_read_esr_el2(void);
+void raw_write_esr_el2(uint32_t esr_el2);
+uint32_t raw_read_esr_el3(void);
+void raw_write_esr_el3(uint32_t esr_el3);
+uint32_t raw_read_esr_current(void);
+void raw_write_esr_current(uint32_t esr);
+uint64_t raw_read_far_el1(void);
+void raw_write_far_el1(uint64_t far_el1);
+uint64_t raw_read_far_el2(void);
+void raw_write_far_el2(uint64_t far_el2);
+uint64_t raw_read_far_el3(void);
+void raw_write_far_el3(uint64_t far_el3);
+uint64_t raw_read_far_current(void);
+void raw_write_far_current(uint64_t far);
+uint64_t raw_read_hcr_el2(void);
+void raw_write_hcr_el2(uint64_t hcr_el2);
+uint64_t raw_read_aa64pfr0_el1(void);
+uint64_t raw_read_mair_el1(void);
+void raw_write_mair_el1(uint64_t mair_el1);
+uint64_t raw_read_mair_el2(void);
+void raw_write_mair_el2(uint64_t mair_el2);
+uint64_t raw_read_mair_el3(void);
+void raw_write_mair_el3(uint64_t mair_el3);
+uint64_t raw_read_mair_current(void);
+void raw_write_mair_current(uint64_t mair);
+uint64_t raw_read_mpidr_el1(void);
+uint32_t raw_read_rmr_el1(void);
+void raw_write_rmr_el1(uint32_t rmr_el1);
+uint32_t raw_read_rmr_el2(void);
+void raw_write_rmr_el2(uint32_t rmr_el2);
+uint32_t raw_read_rmr_el3(void);
+void raw_write_rmr_el3(uint32_t rmr_el3);
+uint32_t raw_read_rmr_current(void);
+void raw_write_rmr_current(uint32_t rmr);
+uint64_t raw_read_rvbar_el1(void);
+void raw_write_rvbar_el1(uint64_t rvbar_el1);
+uint64_t raw_read_rvbar_el2(void);
+void raw_write_rvbar_el2(uint64_t rvbar_el2);
+uint64_t raw_read_rvbar_el3(void);
+void raw_write_rvbar_el3(uint64_t rvbar_el3);
+uint64_t raw_read_rvbar_current(void);
+void raw_write_rvbar_current(uint64_t rvbar);
+uint32_t raw_read_scr_el3(void);
+void raw_write_scr_el3(uint32_t scr_el3);
+uint32_t raw_read_sctlr_el1(void);
+void raw_write_sctlr_el1(uint32_t sctlr_el1);
+uint32_t raw_read_sctlr_el2(void);
+void raw_write_sctlr_el2(uint32_t sctlr_el2);
+uint32_t raw_read_sctlr_el3(void);
+void raw_write_sctlr_el3(uint32_t sctlr_el3);
+uint32_t raw_read_sctlr_current(void);
+void raw_write_sctlr_current(uint32_t sctlr);
+uint64_t raw_read_tcr_el1(void);
+void raw_write_tcr_el1(uint64_t tcr_el1);
+uint32_t raw_read_tcr_el2(void);
+void raw_write_tcr_el2(uint32_t tcr_el2);
+uint32_t raw_read_tcr_el3(void);
+void raw_write_tcr_el3(uint32_t tcr_el3);
+uint64_t raw_read_ttbr0_el1(void);
+void raw_write_ttbr0_el1(uint64_t ttbr0_el1);
+uint64_t raw_read_ttbr0_el2(void);
+void raw_write_ttbr0_el2(uint64_t ttbr0_el2);
+uint64_t raw_read_ttbr0_el3(void);
+void raw_write_ttbr0_el3(uint64_t ttbr0_el3);
+uint64_t raw_read_ttbr0_current(void);
+void raw_write_ttbr0_current(uint64_t ttbr0);
+uint64_t raw_read_ttbr1_el1(void);
+void raw_write_ttbr1_el1(uint64_t ttbr1_el1);
+uint64_t raw_read_vbar_el1(void);
+void raw_write_vbar_el1(uint64_t vbar_el1);
+uint64_t raw_read_vbar_el2(void);
+void raw_write_vbar_el2(uint64_t vbar_el2);
+uint64_t raw_read_vbar_el3(void);
+void raw_write_vbar_el3(uint64_t vbar_el3);
+uint64_t raw_read_vbar_current(void);
+void raw_write_vbar_current(uint64_t vbar);
+
+/* Cache maintenance system instructions */
+void dccisw(uint64_t cisw);
+void dccivac(uint64_t civac);
+void dccsw(uint64_t csw);
+void dccvac(uint64_t cvac);
+void dccvau(uint64_t cvau);
+void dcisw(uint64_t isw);
+void dcivac(uint64_t ivac);
+void dczva(uint64_t zva);
+void iciallu(void);
+void icialluis(void);
+void icivau(uint64_t ivau);
+
+/* TLB maintenance instructions */
+void tlbiall_el1(void);
+void tlbiall_el2(void);
+void tlbiall_el3(void);
+void tlbiall_current(void);
+void tlbiallis_el1(void);
+void tlbiallis_el2(void);
+void tlbiallis_el3(void);
+void tlbiallis_current(void);
+void tlbivaa_el1(uint64_t va);
+
+/* Memory barrier */
+/* data memory barrier */
+#define dmb_opt(opt)  asm volatile ("dmb " #opt : : : "memory")
+/* data sync barrier */
+#define dsb_opt(opt)  asm volatile ("dsb " #opt : : : "memory")
+/* instruction sync barrier */
+#define isb_opt(opt)  asm volatile ("isb " #opt : : : "memory")
+
+#define dmb() dmb_opt(sy)
+#define dsb() dsb_opt(sy)
+#define isb() isb_opt()
+
+/* Clock */
+void set_cntfrq(uint32_t freq);
+
+#endif //__ARCH_LIB_HELPERS_H__