diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2013-06-19 12:39:52 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-12-05 00:38:37 +0100 |
| commit | 6a7dd08b1666758de339ff8096d542a3f4499053 (patch) | |
| tree | d6bce244812136e7e8f281f7822293b7c7c04fb2 /payloads/libpayload/include | |
| parent | 9531692ee18553098b951d8bf5a2eaf46e4d76f5 (diff) | |
| download | coreboot-6a7dd08b1666758de339ff8096d542a3f4499053.tar.xz | |
libpayload: sync ARMv7 arch/io.h with coreboot
On ARMv7 we need to carefully add memory barriers to
all memory read and write operations. This change
brings libpayload in sync with what coreboot is doing.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Ie9c30b0f0d30531c5f9d99c2729246a86b8cec26
Reviewed-on: https://gerrit.chromium.org/gerrit/59294
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/4316
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'payloads/libpayload/include')
| -rw-r--r-- | payloads/libpayload/include/armv7/arch/io.h | 46 |
1 files changed, 40 insertions, 6 deletions
diff --git a/payloads/libpayload/include/armv7/arch/io.h b/payloads/libpayload/include/armv7/arch/io.h index 807dc1d2fb..8948e133ef 100644 --- a/payloads/libpayload/include/armv7/arch/io.h +++ b/payloads/libpayload/include/armv7/arch/io.h @@ -31,12 +31,46 @@ #ifndef _ARCH_IO_H #define _ARCH_IO_H -#define readb(_a) (*(volatile unsigned char *) (_a)) -#define readw(_a) (*(volatile unsigned short *) (_a)) -#define readl(_a) (*(volatile unsigned int *) (_a)) +#include <stdint.h> +#include <arch/cache.h> -#define writeb(_v, _a) (*(volatile unsigned char *) (_a) = (_v)) -#define writew(_v, _a) (*(volatile unsigned short *) (_a) = (_v)) -#define writel(_v, _a) (*(volatile unsigned int *) (_a) = (_v)) +static inline uint8_t readb(volatile void *_a) +{ + dmb(); + return *(volatile uint8_t *)_a; +} + +static inline uint16_t readw(volatile void *_a) +{ + dmb(); + return *(volatile uint16_t *)_a; +} + +static inline uint32_t readl(volatile void *_a) +{ + dmb(); + return *(volatile uint32_t *)_a; +} + +static inline void writeb(uint8_t _v, volatile void *_a) +{ + dmb(); + *(volatile uint8_t *)_a = _v; + dmb(); +} + +static inline void writew(uint16_t _v, volatile void *_a) +{ + dmb(); + *(volatile uint16_t *)_a = _v; + dmb(); +} + +static inline void writel(uint32_t _v, volatile void *_a) +{ + dmb(); + *(volatile uint32_t *)_a = _v; + dmb(); +} #endif |