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authorDuncan Laurie <dlaurie@chromium.org>2016-09-12 11:26:45 -0700
committerAaron Durbin <adurbin@chromium.org>2016-09-14 22:24:19 +0200
commitfbce31a2cc560a316ed6aadac3e8e5c95a095178 (patch)
tree82cd78ef5118d4e02f4bfcb226e563105edbda1c /payloads/libpayload/liblz4/lz4.c.inc
parentf8a7b2c008f45e91e8bc52fbe2d4e0083dab250b (diff)
downloadcoreboot-fbce31a2cc560a316ed6aadac3e8e5c95a095178.tar.xz
drivers/i2c/tpm: Clean up handling of command ready
The TPM driver was largely ignoring the meaning of the command ready bit in the status register, instead just arbitrarily sending it at the end of every receive transaction. Instead of doing this have the command ready bit be set at the start of a transaction, and only clear it at the end of a transaction if it is still set, in case of failure. Also the cr50 function to wait for status and burst count was not waiting the full 2s that the existing driver does so that value is increased. Also, during the probe routine a delay is inserted after each status register read to ensure the TPM has time to actually start up. Change-Id: I1c66ea9849e6be537c7be06d57258f27c563c1c2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16591 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Diffstat (limited to 'payloads/libpayload/liblz4/lz4.c.inc')
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