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authorIonela Voinescu <ionela.voinescu@imgtec.com>2015-01-19 02:41:49 +0000
committerPatrick Georgi <pgeorgi@google.com>2015-03-21 11:09:22 +0100
commit367331161995e7cbaa507bd24a71a28bc97c4834 (patch)
tree3b5ebc236027fe4f9861ba528c791a44d9e56171 /payloads/libpayload
parentbde2081e753b90734af9f198b1ae84d26930363d (diff)
downloadcoreboot-367331161995e7cbaa507bd24a71a28bc97c4834.tar.xz
libpayload: mips: add SOC CPU frequency
Add CPU frequency corresponding to SOC. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected. BRANCH=none Change-Id: I05458070a15c6cf1ef0fc2104715a63902a38887 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4afe332bcc41afeb7e31e918e345c3336f7dc604 Original-Change-Id: I55b788faf7984bafc2509cac69867a772c7cb863 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241427 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'payloads/libpayload')
-rw-r--r--payloads/libpayload/arch/mips/timer.c21
1 files changed, 17 insertions, 4 deletions
diff --git a/payloads/libpayload/arch/mips/timer.c b/payloads/libpayload/arch/mips/timer.c
index 1710a322e2..782959b71a 100644
--- a/payloads/libpayload/arch/mips/timer.c
+++ b/payloads/libpayload/arch/mips/timer.c
@@ -19,6 +19,10 @@
#include <libpayload.h>
#include <arch/cpu.h>
+#include <arch/io.h>
+
+#define PISTACHIO_CLOCK_SWITCH 0xB8144200
+#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002
/**
* @ingroup arch
@@ -34,10 +38,19 @@ u32 cpu_khz;
unsigned int get_cpu_speed(void)
{
if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON)
- cpu_khz = 50000U; /* FPGA board */
- /* else {
- * TODO find CPU frequency on the real SOC
- } */
+ cpu_khz = 50000; /* FPGA board */
+ else {
+ /* If MIPS PLL external bypass bit is set, it means
+ * that the MIPS PLL is already set up to work at a
+ * frequency of 550 MHz; otherwise, the crystal is
+ * used with a frequency of 52 MHz
+ */
+ if (read32(PISTACHIO_CLOCK_SWITCH) &
+ MIPS_EXTERN_PLL_BYPASS_MASK)
+ cpu_khz = 550000;
+ else
+ cpu_khz = 52000;
+ }
return cpu_khz;
}