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| author | Xavi Drudis Ferran <xdrudis@tinet.cat> | 2011-02-28 00:10:37 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2011-02-28 00:10:37 +0000 |
| commit | adb23a51f5f711d10798a0bcddf4764a5dc0ae7c (patch) | |
| tree | bdd085f43754f7d1e54a429a30c8a8557b63451c /payloads/libpayload | |
| parent | 1f4fffb9ccaa3d145b66ddc3e57109cfe8f9fef7 (diff) | |
| download | coreboot-adb23a51f5f711d10798a0bcddf4764a5dc0ae7c.tar.xz | |
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Bring F3xD4 (Clock/Power Control Register 0) more in line
with BKDG i more cases. It requires looking at the CPU package type
so I add a function for that (in the wrong place?) and some
new constants
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6395 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'payloads/libpayload')
0 files changed, 0 insertions, 0 deletions